Features: • Single 5.0 V read, write, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP (Package suffix: PFTN Normal Bend Type, PFTR Reversed Bend Type)
44-pin SOP (Package suffix: PF)
• Minimum 100,000 write/erase cycles
• High performance
55 ns maximum access time
• Sector erase architecture
One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Low Vcc write inhibit3.2 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Hardware RESET pin
Resets internal state machine to the read mode
• Sector protection
Hardware method disables any combination of sectors from write or erase operations
• Temporary sector unprotection
Hardware method temporarily enables any combination of sectors from write on erase operations.Pinout
SpecificationsStorage Temperature ...........................................................................................55°C to +125°C
Ambient Temperature with Power Applied .............................................................40°C to +85°C
Voltage with respect to Ground All pins except A9, OE, RESET (Note 1) ...................2.0 V to +7.0 V
VCC (Note 1) .............................................................................................................2.0 V to +7.0 V
A9, OE, RESET (Note 2) ...........................................................................................2.0 V to +13.5 V
Notes: 1. Minimum DC voltage on input or I/O pins are 0.5 V. During voltage transitions, inputs may negative overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are VCC +0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns.
2. Minimum DC input voltage on A9, OE, RESET pins are 0.5 V. During voltage transitions, A9, OE, RESET pins may negative overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9, OE, RESET pins are +13.0 V which may positive overshoot to 13.5 V for periods of up to 20 ns. Voltage difference between input voltage and power supply. (VIN - VCC) do not exceed 9 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DescriptionThe MBM29F200BC-70 is a 2M-bit, 5.0 V-only Flash memory organized as 256K bytes of 8 bits each or 128K words of 16 bits each. The MBM29F200TC/BC is offered in a 48-pin TSOP and 44-pin SOP packages. This device is designed to be programmed in-system with the standard system 5.0 V VCC supply. 12.0 V VPP is not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. The standard MBM29F200TC/BC offers access times 55 ns and 90 ns allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls.
The MBM29F200BC-70 is pin and command set compatible with JEDEC standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from12.0 V Flash or EPROM devices.
The MBM29F200BC-70 is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in less than 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.
A sector is typically erased and verified in 1.0 second (if already completely preprogrammed.).
The devices also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29F200BC-70 is erased when shipped from the factory.
The devices features single 5.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode.
Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29F200BC-70 memory electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one
byte/word at a time using the EPROM programming mechanism of hot electron injection.
MBM29F200BC-70 Data Sheet
