Features: • Single 5.0 V read, program and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard byte-wide pinouts
32-pin PLCC (Package suffix: PD)
32-pin TSOP(I) (Package suffix: PF)
32-pin TSOP(I) (Package suffix: PFTN Normal Bend Type, PFTR Reversed Bend Type)
• Minimum 100,000 write/erase cycles
• High performance
55 ns maximum access time
• Sector erase architecture
8 equal size sectors of 64K bytes each
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Embedded Erase™ Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program™ Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Low VCC write inhibit £ 3.2 V
• Sector protection
Hardware method disables any combination of sectors from write or erase operations
• Erase Suspend/Resume
Suspends the erase operation to allow a read data in another sector within the same devicePinout
SpecificationsStorage Temperature .............................................................................. 55°C to +125°C
Ambient Temperature with Power Applied ................................................. 40°C to +85°C
Voltage with Respect to Ground All pins except A9, OE (Note 1).................. 2.0 V to +7.0 V
VCC (Note 1) ................................................................................................ 2.0 V to +7.0 V
A9, OE (Note 2) .......................................................................................... 2.0 V to +13.5 V
Notes: 1. Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions, inputs may negative overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is VCC +0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns.
2. Minimum DC input voltage on A9 and OE pins are 0.5 V. During voltage transitions, A9 and OE pins maynegative overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9 and OE pins are +13.5 V which may overshoot to 14.0 V for periods of up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DescriptionThe MBM29F040C-55 is a 4M-bit, 5.0 V-only Flash memory organized as 512K bytes of 8 bits each. The MBM29F040C is offered in a 32-pin PLCC and 32-pin TSOP(I) package. This device is designed to be programmed in-system with the standard system 5.0 V VCC supply. A 12.0 V VPP is not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers.
The standard MBM29F040C-55 offers access times 55 ns and 90 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls.
The MBM29F040C-55 is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 V Flash or EPROM devices.
The MBM29F040C-55 is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in less than 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.
Any individual sector is typically erased and verified in 1 second. (If already completely preprogrammed.) The device also features a sector erase architecture.
The sector mode allows for 64K byte sectors of memory to be erased and reprogrammed without affecting other sectors. The MBM29F040C-55 is erased when shipped from the factory.
The device features single 5.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7 or by the Toggle Bit feature on DQ6. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode.
Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability and cost effectiveness. The MBM29F040C-55 memory electrically erases the entire chip or all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.
MBM29F040C-55 Data Sheet
