MBM29F004TC

• Single 5.0 V read, write, and erase Minimizes system level power requirements
• Compatible with JEDEC-standard commands Pinout and software compatible with single-power supply Flash Superior inadvertent write protection
• 32-pin TSOP (1) (Package Suffix : PFTN-Normal Bend Type, PFTR-Reverse Bend Type) 32-pin PLCC (Package Suffix : PD)
• Minimum 100,000 write/erase cycles
• High performance 70 ns maximum access time
• Flexible sector erase architecture One 16 K byte, two 8 K bytes, one 32 K byte, and seven 64 K bytes sectors Any combination of sectors can be erased. Also supports full chip erase.
• Embedded Erase™* Algorithms Automatically pre-programs and erases the chip or any sector
• Embedded Program™* Algorithms Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Low VCC write inhibit £ 3.2 V
• Erase Suspend/Resume Supports reading or programming data to a sector not being erased
• Sector Protection Hardware sector protect that disables any combination of sectors from write or erase operations
• Temporary Sector Unprotection Temporary sector unprotection via the command sequence
• Boot Code Sector Architecture
• Fast Programming
• Extended Sector Protection

The MBM29F004TC/BC is a 4 M-bit, 5.0 V-Only Flash memory organized as 512 K bytes of 8 bits each. The MBM29F004TC/BC is offered in a 32-pin TSOP (1) and 32-pin QFJ (PLCC) packages. This device is designed to be programmed in-system with the standard system 5.0 V VCC supply. A 12.0 V VPP is not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers.
 
The standard MBM29F004TC/BC offers access times between 70 ns and 90 ns allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE) , write enable (WE) , and output enable (OE) controls.

The MBM29F004TC/BC is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 V Flash or EPROM devices.