Features: •Single 3.0 V read, program, and eraseMinimizes system level power requirements
•Simultaneous operationsRead-while-Erase or Read-while-Program
•Compatible with JEDEC-standard commandsUses same software commands as E2PROMs
•Compatible with JEDEC-standard world-wide pinouts (Pin compatible with MBM29LV800TA/BA)48-pin TSOP(I) (Package suffix: PFTN Normal Bend Type, PFTR Reversed Bend Type)48-ball FBGA (Package suffix: PBT)
•Minimum 100,000 program/erase cycles
•High performance70 ns maximum access time
•Sector erase architectureTwo 16K byte, four 8K bytes, two 32K byte, and fourteen 64K bytes.Any combination of sectors can be concurrently erased. Also supports full chip erase.
•Boot Code Sector ArchitectureT = Top sectorB = Bottom sector
•Embedded EraseTM AlgorithmsAutomatically pre-programs and erases the chip or any sector
•Embedded Program TM Algorithms Automatically writes and verifies data at specified address
•Data Polling and Toggle Bit feature for detection of program or erase cycle completion
•Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion
•Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode.
•Low VCC write inhibit 2.5 V
•Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same devicePinout
SpecificationsAmbient Temperature (TA)................................................................................40°C to +85°C
VCC Supply Voltages
MBM29LV800TA/BA-70.........................................................................................+3.0 V to +3.6 V
MBM29LV800TA/BA-90/-12...................................................................................+2.7 V to +3.6 VDescriptionThe MBM29DL800TA/BA are a 8M-bit, 3.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K words of 16 bits each. The MBM29DL800TA/BA are offered in a 48-pin TSOP(I) and 48-ball FBGA packages. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
MBM29DL800TA/BA provides simultaneous operation which can read a data while program/erase. The simultaneous operation architecture provides simultaneous operation by dividing the memory space into two banks. The device can allow a host system to program or erase in one bank, then immediately and simultaneously read from the other bank.
The standard MBM29DL800TA/BA offer access times 70 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable (OE) controls.
The MBM29DL800TA/BA are pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29DL800TA/BA are programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the devices automatically time the erase pulse widths and verify proper cell margin.
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29DL800TA/BA are erased when shipped from the factory.
The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the devices internally reset to the read mode.
Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29DL800TA/BA memories electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.
MBM29DL800TA Data Sheet
