MBM29DL400BC-55

Storage Temperature .............................................................................................55°C to +125°C
Ambient Temperature with Power Applied ................................................................40°C to +85°C
Voltage with respect to Ground All pins except A₉, OE, RESET (Note 1) ................0.5 V to V_CC+0.5 V
V_CC (Note 1) ................................................................................................................0.5 V to +5.5 V
A₉, OE, and RESET (Note 2) .......................................................................................0.5 V to +13.0 V
Notes: 1. Minimum DC voltage on input or I/O pins are 0.5 V. During voltage transitions, inputs may negative overshoot V_SS to 2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are V_CC +0.5 V. During voltage transitions, outputs may positive overshoot to V_CC +2.0 V for periods of up to 20 ns.
2. Minimum DC input voltage on A₉, OE and RESET pins are 0.5 V. During voltage transitions, A₉, OE and RESET pins may negative overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC input voltage on A₉, OE and RESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of up to 20 ns. when V_CC is applied.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

The MBM29DL400BC-55 are a 4M-bit, 3.0 V-only Flash memory organized as 512K bytes of 8 bits each or 256K words of 16 bits each. The MBM29DL400TC/BC are offered in a 48-pin TSOP(I) package. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.

MBM29DL400BC-55 provides simultaneous operation which can read a data while program/erase. The simultaneous operation architecture provides simultaneous operation by dividing the memory space into two banks. The device can allow a host system to program or erase in one bank, then immediately and simultaneously read from the other bank.

The standard MBM29DL400TC/BC offer access times 55 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable (OE) controls.

The MBM29DL400BC-55 are pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29DL400BC-55 are programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the devices automatically time the erase pulse widths and verify proper cell margin.

A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)

The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29DL400BC-55 are erased when shipped from the factory.

The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low V_CC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ₇, by the Toggle Bit feature on DQ₆, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the devices internally reset to the read mode.

Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29DL400BC-55 memories electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.