MBM29DL32XTE

• 0.23 mm Process Technology
• Simultaneous Read/Write operations (dual bank) Multiple devices available with different bank sizes (Refer to Table 1) Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program
• Single 3.0 V read, program, and erase Minimizes system level power requirements
• Compatible with JEDEC-standard commands Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(I) (Package suffix: TN Normal Bend Type, TR Reversed Bend Type) 63-ball FBGA (Package suffix: PBT
• Minimum 100,000 program/erase cycles
• High performance 80 ns maximum access time
• Sector erase architecture
   Eight 4K word and sixty-three 32K word sectors in word mode
  Eight 8K byte and sixty-three 64K byte sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
  T = Top sector
  B = Bottom sector
• Hidden ROM (Hi-ROM) region 64K byte of Hi-ROM, accessible through a new "Hi-ROM Enable" command sequence Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status At VIH, allows removal of boot sector protection At VAcc, increases program performance
• Embedded EraseTM*Algorithms Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion
• Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit £ 2.5 V
• Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)

Notes : 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot Vss to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is Vcc+ 0.5 V. During voltage transitions, input or I/O pins may overshoot to Vcc+ 2.0 V for periods of up to 20 ns.
2. Minimum DC input voltage on A9, OE and RESET pins is -0.5 V. During voltage transitions, A9, OE and RESET pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN - Vcc) does not exceed +9.0 V. Maximum DC input voltage on A9, OE and RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns.
3. Minimum DC input voltage onWP/Acc pin is -0.5 V. During voltage transitions, WP/Acc pin may undershoot Vss to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/Acc pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns when Vcc is applied.

The MBM29DL32XTE/BE are a 32M-bit, 3.0 V-only Flash memory organized as 4M bytes of 8 bits each or 2M words of 16 bits each. These devices are designed to be programmed in-system with the standard system 3.0 V Vccsupply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.

MBM29DL32XTE/BE are organized into two banks, Bank 1 and Bank 2, which can be considered to be two separate memory arrays as far as certain operations are concerned. These devices are the same as Fujitsu's standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank.