MBM29DL32XTD/BD

• 0.33 mm Process Technology
• Simultaneous Read/Write operations (dual bank)
Multiple devices available with different bank sizes (Refer to Table 1)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations
Read-while-erase
Read-while-program
• Single 3.0 V read, program, and erase Minimizes system level power requirements

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Notes: 1. Minimum DC voltage on input or I/O pins are 0.5 V. During voltage transitions, inputs may negative overshoot V_SS to 2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are V_CC +0.5 V. During voltage transitions, outputs may positive overshoot to V_CC +2.0 V for periods of up to 20 ns.
2. Minimum DC input voltage on A9, OE and RESET pins are 0.5 V. During voltage transitions, A₉, OE and RESET pins may negative overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9, OE and RESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of up to 20 ns. when V_CC is applied.
3. Minimum DC input voltage on WP/ACC pin is 0.5 V. During voltage transitions, WP/ACC pin may negative overshoot V_SS to 2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin iis +10.5V which may positive overshoot to +10.5V for periods of up to 20ns when Vcc is applied.

The MBM29DL32XTD/BD is a 32M-bit, 5.0 V-Only Flash memory organized as 4M bytes of 8 bits each. The 2M bytes of data is divided into 64 sectors of 64K bytes for flexible erase capability. The 8 bit of data will appear on DQ0 to DQ7. The MBM29DL32XTD/BD is offered in a 40-pin TSOP package. This device is designed to be programmed insystem with the standard system 5.0 V V_CC supply. A 12.0 V V_PP is not required for program or erase operations. The device can also be reprogrammed in standard EPROM programmers.

The standard MBM29F033C offers access times between 70 ns and 120 ns allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls.

The MBM29DL32XTD/BD is command set compatible with JEDEC standard single-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 V Flash or EPROM devices.

The MBM29DL32XTD/BD is programmed by executing the program command sequence. This will invoke the Embedded ProgramTM Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Each sector can be programmed and verified in less than 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded EraseTM Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

This device also features a sector erase architecture. The sector erase mode allows for sectors of memory to be erased and reprogrammed without affecting other sectors. Asector is typically erased and verified within one second (if already completely preprogrammed). The MBM29DL32XTD/BD is erased when shipped from the factory.

The MBM29DL32XTD/BD device also features hardware sector group protection. This feature will disable both program and erase operations in any combination of eight sector groups of memory. A sector group consists of four adjacent sectors grouped in the following pattern: sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, 28-31, 32- 35, 36-39, 40-43, 44-47, 48-51, 52-55, 56-59, and 60-63.

Fujitsu has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of time to read data from or program data to a non-busy sector. Thus, true background erase can be achieved.

The device features single 5.0 V power supply operation for both read and program functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations during power transitions. The end of program or erase is detected by Data Polling of DQ₇, or by the Toggle Bit I feature on DQ₆ or RY/BY output pin. Once the end of a program or erase cycle has been completed, the device automatically resets to the read mode.

The MBM29DL32XTD/BD also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program or Embedded Erase operations will be terminated. The internal state machine will then be reset into the read mode. The RESET pin may be tied to the system reset circuity. Therefore, if a system reset occurs during the Embedded Program or Embedded Erase operation, the device will be automatically reset to a read mode. This will enable the system microprocessor to read the boot-up firmware from the Flash memory.

Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29DL32XTD/BD memory electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.