MB86613

Features: 1. 1394 serial bus controller Unit• Compliant with IEEE 1394-1995 Standard• PHYsical and LINK layer modules integrated on a single chip• Three internal ports• Transfer rates of S100, S200, and S400 supported• On-chip PLL for generating 400-MHz (PHY) and 50-M...

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SeekIC No. : 004413602 Detail

MB86613: Features: 1. 1394 serial bus controller Unit• Compliant with IEEE 1394-1995 Standard• PHYsical and LINK layer modules integrated on a single chip• Three internal ports• Trans...

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Part Number:
MB86613
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

1. 1394 serial bus controller Unit
• Compliant with IEEE 1394-1995 Standard
• PHYsical and LINK layer modules integrated on a single chip
• Three internal ports
• Transfer rates of S100, S200, and S400 supported
• On-chip PLL for generating 400-MHz (PHY) and 50-MHz (LINK) CLK signals
• Built-in cycle master function
• Bus management CSR (control and status register)
• Six-conductor cable supported
• Internal transceiver and comparator
• Internal comparator for cable power detection
2. Context program controller unit
• Compliant with Open HCI Standard (Draft 1.00)
• Thirteen context program controllers integrated:
• Internal 6-KB FIFO buffers
3. PCI bus controller unit
• Compliant with PCI Standard (Revision 2.2)
• On-chip 32-bit DMA controller
• Built-in power management function (Compliant with PCI bus power management standard version 1.0)
• Built-in alignment function
• Built-in byte swap function
• Operating frequency of up to 33 MHz
• Internal parallel ROM interface
• Internal serial ROM interface
• Internal universal (5/3.3 V shared) PCI buffer
4. Physical specifications
• Package: LQFP144 (FPT-144P-M08), FBGA176 (BGA-176P-M02)
• Power-supply voltage: Dual system for 5 V (± 5%) and 3.3 V (± 5%)
5. Reference standards
• IEEE Standard for a High Performance 1394-1995
• 1394 Open Host Controller Interface Specification (Release 1.00)
• PCI Specification (Revision 2.2)
• PCI Bus Power Management Interface Specification (Version 1.0)



Pinout

  Connection Diagram


Specifications

Parameter Symbol Value Unit
Min. Max.
Power supply voltage at 5 V* VDD VSS 0.5 6.0 V
at 3 V* 4.0
Input voltage VI VSS 0.5 VDD + 0.5 V
Output voltage VO VSS 0.5 VDD + 0.5 V
Storage temperature TST -55 +125 °C
Operating temperature Top -40 +85 °C

*1 : The voltages are bassed on VSS = 0 V.
*2 : The 5 V power supply is the voltage applied at the VDD5/3 and VDD5 power supply pins.
*3 : The 3 V power supply is the voltage applied at the DVDD3 and AVDD3 power supply pins.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

 




Description

The MB86613 a high-performance, host-bus (PCI) and serial-bus (1394) controller chip for controlling transfer between the PCI and 1394 buses. This chip conforms to the PCI Standard Version 2.1 for PCI control, the IEEE 1394-1995 Standard for 1394 control, and the Open HCI Standard Version 1.0 for PCI-1394 control The MB86613 consists of the PCI/DMA, OHCI, and 1394 blocks. The PCI/DMA block provides PCI bus protocol control. The block has the slave function for responding register access from a bus master, the master function for issuing transfer requests from the MB86613 as the bus master, the power management function (compliant with PCI bus power management standard version 1.0), and the interfaces to BIOS ROM and PCI configuration ROM.

The MB86613 OHCI block analyzes context programs pre-stored in host memory to store the packet to be sent out from host memory to the FIFO buffer or to store the received packet from the FIFO buffer to host memory. The 1394 block incorporates the LINK layer module, PHYsical layer module, 1394 transceiver, comparator, and PLL, providing 1394 bus protocol control. The block converts the packet stored in the FIFO buffer to serial data and send it onto the 1394 bus or converts the packet received from the 1394 bus to parallel data and stores it in the FIFO buffer.

For packet transmission and reception, the MB86613 supports a transfer rate of up to S400. In addition, the cycle master function is provided for automatic management of isochronous cycles. The chip reserves 6K bytes of FIFO memory. The on-chip dual port RAM contains 3K bytes for packet transmission and 3K bytes for packet reception.

The MB86613 uses the 0.35 micron CMOS process technology, integrating the LINK and PHYsical layer modules on this single chip to reduce the packaging area and power consumption.

The chip has a dual-voltage system to support both 5 V (PCI/DMA) and 3.3 V (1394) power-supply voltages. Note that the PCI/DMA block can operate at 3.3 V. The package is a plastic package of LQFP144 or FBGA176.




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