MA17503

· Mil-Std-1750A Istructio Set Architecture
· Full Performace over Military Temperature Rage (-55°C to +125°C)
· Radiatio Hard CMOS/SOS Techology
· Iterrupt Hadler
· 9 User Iterrupt Iputs
· Pedig Iterrupt Register
· Iterrupt Mask Register
· Iterrupt Priority Ecoder
· Fault Hadler
· 8 User Faults Iputs
· Fault Register
· Timers
· Timer A
· Timer B
· Trigger-Go
· DMA Iterface
· Iterface Discretes
· Normal Power-Up
· Start-Up ROM Eable
· Cofiguratio Word Eable
· Implemets 26 MIL-STD-1750A Specified l/O Commads
· MAS281 Itegrated Built-l Self Test
· TTL Compatible System Iterface

The MA17503 Interrupt Unit (IU) is a component of the GPS MAS281 chip set. This chip set implements the full MIL-STD-1750A instruction set architecture. Other chips in the set include the MA17501 Execution Unit (EU) and MA17502 Control Unit (CU). Also available is the peripheral MA31751 Memory Management Unit/Block Protection Unit (MMU(BPU)). Figure 1 depicts the relationship between the chip set components.

The IU of MA17503 provides the interrupt and fault handling interfaces for the chip set. The IU also provides the DMA control interface logic, contains interval Timers A and B, the Trigger-Go Counter, the Bus Fault Timeout timer, and decodes all MILSTD-1750A specified l/O commands in support of these functions. The EU provides the arithmetic and logical computation resources for the chip set. The EU and IU are each controlled by microcode from the CU. The MMU(BPU) may be configured to provide either 1M-word memory management (MMU) and/or 1K-word memory block write protection (BPU) functions.

As shown in Figure 1, the MAS281 is the minimum processor configuration consisting of an Execution Unit, a Control Unit, and an Interrupt Unit. This configuration is capable of accessing a 64K-word address space. Addition of a MMU configured MA31751 allows access to a 1M-word address space. Addition of a BPU configured MA31751 provides hardware support for 1K-word memory block write protection.

The IU, as with all components of the MAS281 chip set, is fabricated with CMOS/SOS process technology. Detailed descriptions of the lUs companion chips are provided in separate data sheets. Additional discussions on chip set system considerations, interconnection details, and Digital Avionics Instruction Set (DAIS) mix benchmarking analysis are provided in separate application notes.