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M74HCT75

Features: `HIGH SPEED: tPD = 21ns (TYP.) at VCC = 4.5V`LOW POWER DISSIPATION: ICC = 1mA(MAX.) at TA=25°C`COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX)`BALANCED PROPAGATION DELAYS: tPLH tPHL`SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)`PIN AND FUNCTION COMPATIBLE WITH 74 ...

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SeekIC No. : 004407279 Detail

M74HCT75: Features: `HIGH SPEED: tPD = 21ns (TYP.) at VCC = 4.5V`LOW POWER DISSIPATION: ICC = 1mA(MAX.) at TA=25°C`COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX)`BALANCED PROPAGATION DELAYS: t...

M74HCT75 Data Sheet

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Part Number:
M74HCT75
Supply Ability:
5000

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Product Details

Description



Features:

`HIGH SPEED:
  tPD = 21ns (TYP.) at VCC = 4.5V
`LOW POWER DISSIPATION:
  ICC = 1mA(MAX.) at TA=25°C
`COMPATIBLE WITH TTL OUTPUTS :
  VIH = 2V (MIN.) VIL = 0.8V (MAX)
`BALANCED PROPAGATION DELAYS:
  tPLH tPHL
`SYMMETRICAL OUTPUT IMPEDANCE:
  |IOH| = IOL = 4mA (MIN)
`PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 75


Pinout

Connection Diagram


Specifications

Symbol Parameter Value Unit
VCC Supply Voltage -0.5 to +7 V
VI DC Input Voltage -0.5 to VCC + 0.5 V
VO DC Output Voltage -0.5 to VCC + 0.5 V
IIK DC Input Diode Current ± 20 mA
IOK DC Output Diode Current ± 20 mA
IO DC Output Current ± 25 mA
ICC or IGND DC VCC or Ground Current ± 50 mA
PD Power Dissipation 500(*) mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature (10 sec) 300 °C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C




Description

The M74HCT75 is an high speed CMOS 4 BIT D TYPE LATCH fabricated with silicon gate C2MOS technology.

The M74HCT75 contains two groups of 2 bit latches controlled by an enable input (G1·2 or G3·4). These two latch groups can be used in different circuits. Each latch has Q and Q outputs (1Q - 4Q and 1Q - 4Q). The data applied to the data input is transferred to the Q and Q outputs when the enable input is taken high and the outputs will follow the data input as long as the enable input is kept high. When the enable input is taken low, the information data applied to the data input is retained at the outputs. The M74HCT75 is designed to directly interface HSC2MOS systems with TTL and NMOS components.

All inputs of M74HCT75 are equipped with protection circuits against static discharge and transient excess voltage.




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