M74HCT574

.HIGH SPEED
f_MAX = 62 MHz (TYP.) AT V_CC = 5 V
.LOWPOWER DISSIPATION
I_CC = 4 mA (MAX.) AT T_A = 25 °C
.COMPATIBLE WITH TTL OUTPUTS
V_IH = 2V (MIN.) V_IL = 0.8V (MAX)
.OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
.SYMMETRICAL OUTPUT IMPEDANCE
I_OL = |I_OH|= 6 mA (MIN.)
. BALANCEDPROPAGATION DELAYS
t_PLH = t_PHL
.PIN AND FUNCTION COMPATIBLE WITH 54/74LS564/574

AbsoluteMaximumRatings are those values beyond whichdamage tothe device may occur. Functional operation under these condition isnotimplied.
(*) 500 mW: @ 65 ^oC derate to 300mWby 10mW/^oC: 65 ^oC to85^oC

The M54/74HCT564 and M54HCT574 are high speed CMOS OCTAL D-TYPE FLIPFLOP WITH 3- STATEOUTPUTS fabricated in silicon gate C²MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power comsuption. These 8-bit D-type flip-flops are controlled by a clock input(CK) and an ouput enable input (OE).On the positive transition of the clock, the Qoutputs willbe set to thelogic statethatwere setup at the D inputs (HCT574) or their complements (HCT564).

While the OE input of M54/74HCT564 and M54HCT574 is low, the eight outputs will b in a normal logic state (high or low logic level), and while high level, the outputs will be in a high impedance state. The output control does not affect the internal operation of flip-flops. That is, the old data can be retained or the new data can be entered even while the outputs are off. The application engineer has a choice of combination of inverting and non-inverting outputs. The 3-state output configuration and the wide choice of outline make bus-organized systems simple. All inputs are equipped with protection circuits against static discharge and transient excess voltage. This integrated circuit has input and output characteristics that are fully compatible with 54/74 LSTTL logic families. M54/74HCT devices are designed to directly interface HSC²MOS systems with TTL and NMOS components. They are also plug in replacements for LSTTL devices giving a reduction of power consumption.