M74HCT165

Features: HIGH SPEED tPD = 17 ns (TYP.) AT VCC = 5 V LOWPOWER DISSIPATION ICC = 4 mA (MAX.) AT TA = 25OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS BALANCEDPROPAGATION DELAYS tPLH = tPHL SYMMETRICAL OUTPUT IMPEDANCE IOL = IOH = 4 mA (MIN.) COMPATIBLE WITH TTL OUTPUTS VIH = 2 V (MIN.) VIL = 0.8 V (MAX.)PI...

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M74HCT165 Picture
SeekIC No. : 004407241 Detail

M74HCT165: Features: HIGH SPEED tPD = 17 ns (TYP.) AT VCC = 5 V LOWPOWER DISSIPATION ICC = 4 mA (MAX.) AT TA = 25OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS BALANCEDPROPAGATION DELAYS tPLH = tPHL SYMMETRICAL OUTPUT...

floor Price/Ceiling Price

Part Number:
M74HCT165
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

HIGH SPEED
   tPD = 17 ns (TYP.) AT VCC = 5 V
LOWPOWER DISSIPATION
   ICC = 4 mA (MAX.) AT TA = 25 
OUTPUT DRIVE CAPABILITY
   10 LSTTL LOADS
BALANCEDPROPAGATION DELAYS
   tPLH = tPHL
SYMMETRICAL OUTPUT IMPEDANCE
   IOL = IOH = 4 mA (MIN.)
COMPATIBLE WITH TTL OUTPUTS
   VIH = 2 V (MIN.) VIL = 0.8 V (MAX.)
PIN AND FUNCTION COMPATIBLE
   WITH 54/74LS165



Pinout

  Connection Diagram


Description

The M54/74HCT165 is a high speed CMOS 8 BITPISO SHIFT REGISTER fabricated in silicon gateC2MOS technology. It has the same high speedperformance of LSTTL combined with true CMOSlow power consumption. It achives the high speedoperation similar to equivalent LSTTL whilemaintaining the CMOS low power dissipation.This device contains eight clocked master slave RSflip-flops connected as a shift register, with auxiliarygating to provide over-riding asynchronous parallelentry. Parallel data entrens when the shift/load inputis low. The parallel data can change while shift/loadis low, provided that the recommended set-up andhold times are observed. For clocked operation,shift/load must be high. The two clock input performidentically; one can be used as a clock inhibit byapplying a high signal; to permit this operationclocking is accomplished through a 2 input norgates.
To avoid double clocking, however, the inhibit signalshould only go high while the clock is high.Otherwise the rising inhibit signal will cause thesame response as rising clock edge.This integratedcircuit has input and output characteristics that arefully compatible with 54/74 LSTTL logic families.M54/74HCT devices are designed to directlyinterface HSCMOS systems with TTL and NMOScomponents. They are also plug in replacements forLSTTL devices giving a reduction of powerconsumption. All inputs are equipped withprotection circuits against static discharge andtransient excess voltage.




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