M74HCT137

TheM54/74HCT137 isa high speed CMOS3TO8LINE DECODER/LATCH (INVERTING) fabricated in silicon gateC²MOStechnology. Ithas the samehigh speed performance ofLSTTL combinedwith trueCMOSlowpower consumption. This device isa 3 to 8 line decoder with latchesonthe three address inputs.When GL goes fromlow tohigh, the address present at the select inputs (A,B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable pins G1 and G2, control the state of the outputs independently ofthe selector latch-enable inputs. All theoutputs are high unless G1 is high and G2 is low. The HC137 is ideally suited for the implementation of glitch-free decoders in stored-address applications in bus oriented systems. All inputs are equipped with protection circuits against static discharge and transient excess voltage.This integrated circuit has input and output characteristics that are fully compatible with 54/74 LSTTL logic families.M54/74HCT devicesaredesigned todirectlyinterfaceHSC2MOSsystemswithTTL andNMOScomponents. They arealso plug in replacements for LSTTL devices giving a reduction of power consumption.