Features: ·HIGH SPEED tPD = 10 ns (TYP.) AT VCC = 5 V· LOWPOWER DISSIPATION ICC = 2 mA (MAX.) AT TA = 25 °C ·HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.)· OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS· SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) ·BALANCEDPROPAGATION DELAYS tPLH = tPHL ·WI...
M74HC75: Features: ·HIGH SPEED tPD = 10 ns (TYP.) AT VCC = 5 V· LOWPOWER DISSIPATION ICC = 2 mA (MAX.) AT TA = 25 °C ·HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.)· OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS...
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Symbol | Parameter | Value | Unit |
VCC | Supply Voltage | -0.5 to +7 | V |
VI | DC Input Voltage | -0.5 to VCC + 0.5 | V |
VO | DC Output Voltage | -0.5 to VCC + 0.5 | V |
IIK | DC Input Diode Current | ± 20 | mA |
IOK | DC Output Diode Current | ± 20 | mA |
IO | DC Output Current | ± 25 | mA |
ICC or IGND | DC VCC or Ground Current | ± 50 | mA |
PD | Power Dissipation | 500(*) | mW |
Tstg | Storage Temperature | -65 to +150 | °C |
TL | Lead Temperature (10 sec) | 300 | °C |
The M54/74HC75 is a high speed CMOS 4-BIT DTYPELATCHfabricated in silicon gate C2MOStechnology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The M54/74HC75 contains two groups of 2-bit latches controlled by an enable input (G1•2 orG3•4). These two latch groups can be used in different circuits. Each latch has Q and Q outputs (1Q - 4Q and 1Q - 4Q). The data applied to the data input is transfered to the QandQ outputs when the enable input is taken high and the outputs will follow the data input as long as the enable input is kept high. When the enable input is taken low, the information data applied to the data input is retained at the outputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage.