Features: `HIGH SPEED fMAX =73 MHz (TYP.) AT VCC = 5 V `LOWPOWER DISSIPATION ICC = 4 A (MAX.) AT TA = 25 °C `HIGH NOISE IMMUNITY VNIH = VNIL= 28% VCC (MIN.)` OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS `SYMMETRICAL OUTPUT IMPEDANCE |IOH|= IOL = 6 mA (MIN.) ` WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V...
M74HC648: Features: `HIGH SPEED fMAX =73 MHz (TYP.) AT VCC = 5 V `LOWPOWER DISSIPATION ICC = 4 A (MAX.) AT TA = 25 °C `HIGH NOISE IMMUNITY VNIH = VNIL= 28% VCC (MIN.)` OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS `...
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Symbol |
Parameter |
Value |
Unit |
VCC |
Supply Voltage |
-0.5 to +7 |
V |
VI |
DC Input Voltage |
-0.5 to VCC + 0.5 |
V |
VO |
DC Output Voltage |
-0.5 to VCC + 0.5 |
V |
IIK |
DC Input Diode Current |
± 20 |
mA |
IOK |
DC Output Diode Current |
± 20 |
mA |
IO |
DC Output Source Sink Current Per Output Pin |
± 35 |
mA |
ICC or IGND |
DC VCC or Ground Current |
± 70 |
mA |
PD |
Power Dissipation |
500 (*) |
mW |
Tstg |
Storage Temperature |
-65 to +150 |
°C |
TL |
Lead Temperature (10 sec) |
300 |
°C |
The M74HC646/648 are high speed CMOSOCTAL BUS TRANSCEIVERS AND REGISTERS, (3- STATE) fabricated in silicon gate C2MOS technology. They have the same high speed performance of LSTTL combined with trueCMOSlow power consumption.
The M74HC646/648 consist of bus transceiver circuits with 3-state output, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the Aor B bus will be clocked into the registers on the low-to-high transition of the appropriate clock pin (ClockAB- or Clock BA). Enable(G) and direction (DIR) pins are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both.
The select of M74HC646/648 controls (Select AB select BA) can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when enable G is active (low). In the isolation mode (enable G high), "A" data may be stored in one register and/or "B" data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. All inputs are equipped with protection circuits