M74HC595

HIGH SPEED f_MAX = 55 MHz (TYP.) AT V_CC = 5 V
LOWPOWER DISSIPATION I_CC = 4 mA (MAX.) AT T_A = 25 °C
HIGH NOISE IMMUNITY V_NIH = V_NIL = 28 % V_CC (MIN.)
OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS FOR QA TO QH  10 LSTTL LOADS FOR QH'
SYMMETRICAL OUTPUT IMPEDANCE
I_OH| = I_OL = 6 mA (MIN.) FOR QA TOQH
I_OH| = I_OL = 4 mA (MIN.) FOR QH'
BALANCEDPROPAGATION DELAYS t_PLH = t_PHL
WIDE OPERATING VOLTAGE RANGE V_CC (OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE WITH 54/74LS595

The M54/74HC595 is a high speed CMOS 8-BIT SHIFT REGISTERS/OUTPUT LATCHES (3- STATE) fabricated in silicon C²MOS technology. The M54/74HC595 has the same high speed performance of LSTTL combined with true CMOS low power consumption. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has 8 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register.

The shift register of M54/74HC595 has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register.

All inputs are equipped with protection circuits against static discharge and transient excess voltage.