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M74HC563

Features: ` HIGH SPEED: tPD = 13ns (TYP.) at VCC = 6V` LOW POWER DISSIPATION: ICC = 4A(MAX.) at TA=25` HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.)` SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN)` BALANCED PROPAGATION DELAYS: tPLH tPHL` WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to ...

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SeekIC No. : 004407188 Detail

M74HC563: Features: ` HIGH SPEED: tPD = 13ns (TYP.) at VCC = 6V` LOW POWER DISSIPATION: ICC = 4A(MAX.) at TA=25` HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.)` SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL =...

M74HC563 Data Sheet

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Part Number:
M74HC563
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

` HIGH SPEED:
    tPD = 13ns (TYP.) at VCC = 6V
` LOW POWER DISSIPATION:
    ICC = 4A(MAX.) at TA=25
` HIGH NOISE IMMUNITY:
    VNIH = VNIL = 28 % VCC (MIN.)
` SYMMETRICAL OUTPUT IMPEDANCE:
    |IOH| = IOL = 6mA (MIN)
` BALANCED PROPAGATION DELAYS:
    tPLH  tPHL
` WIDE OPERATING VOLTAGE RANGE:
    VCC (OPR) = 2V to 6V
` PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 563


Pinout

Connection Diagram


Specifications

Symbol
Parameter
Value
Unit
VCC
 Supply Voltage
-0.5 to +7
V
VI
 DC Input Voltage
-0.5 to VCC + 0.5
V
VO
 DC Output Voltage
-0.5 to VCC + 0.5
V
IIK
 DC Input Diode Current
± 20
mA
IOK
 DC Output Diode Current
± 20
mA
IO
 DC Output Current
±35
mA
ICC or IGND
 DC VCC or Ground Current
±70
mA
PD
 Power Dissipation
500(*)
mW
Tstg
 Storage Temperature
-65 to +150
TL
 Lead Temperature (10 sec)
300
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional
operation under these conditions is not implied

(*) 500mW at 65; derate to 300mW by 10mW/ from 65 to 85


Description

The M74HC563 is an high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with silicon gate C2MOS technology.

This 8-BIT D-Type latches of M74HC563 is controlled by a latch enable input (LE) and output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data input inversely. When the LE is taken, the Q outputs will be latched inversely at the logic level of D input data. While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while OE is in high level the outputs will be in a high impedance state.

The 3-State output configuration and the wide choice of outline make bus organized system simple.

All inputs are equipped with protection circuits against static discharge and transient excess voltage.




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