Features: .HIGH SPEED fMAX = 73 MHz (TYP.) at VCC = 5V .LOWPOWER DISSIPATION ICC = 4 mA (MAX.) at TA = 25 oC .HIGH NOISE IMMUNITY VNIH= VNIL= 28%VCC (MIN.) .OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS .SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) .BALANCEDPROPAGATION DELAYS tPLH = tPHL .WIDE ...
M74HC4020: Features: .HIGH SPEED fMAX = 73 MHz (TYP.) at VCC = 5V .LOWPOWER DISSIPATION ICC = 4 mA (MAX.) at TA = 25 oC .HIGH NOISE IMMUNITY VNIH= VNIL= 28%VCC (MIN.) .OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS .S...
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Parameter |
Value |
SYMBOL |
UNIT |
Supply Voltage |
-0.5 to +7 |
VCC |
V |
DC Input Voltage |
-0.5 to VCC + 0.5 |
VI |
V |
DC Output Voltage |
-0.5 to VCC + 0.5 |
VC |
V |
DC Input Diode Current |
± 20 |
IIK |
mA |
DC Output Diode Currente |
± 20 |
Tj |
mA |
DC Output Source Sink Current Per Output Pin |
± 25 |
Tstg |
mA |
DC VCC or Ground Current |
± 50 |
TSTG |
oC |
Power Dissipation |
500 (*) |
PD |
mW |
Storage Temperature |
-65 to +150 |
TSTG |
oC |
Lead Temperature (10 sec) |
300 |
VEBO |
°C |
The M54/74HC4020/HC4040 are high speed CMOS 14/12-STAGE BINARY COUNTER fabricated in silicon gate C2MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low consumption. A clear input is used to reset the counter to the all low level state.Ahigh level on CLEAR accomplishes the reset function. A negative transition on the CLOCK input increments the counter by one. For HC4020 twelve kind od divided output are provided; 1st and 4th stage to 14th stage.
The maximum division of M54/74HC4020/HC4040 available at last stage is 1/16384 x fIN at clock. For HC4040 each division stage has an output; the final frequency is 1/4096 x fIN. All inputs are equipped with protection circuits against static discharge and transient excess voltage.