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M74HC4017

Features: ·HIGH SPEED tPD =21 ns (TYP.) AT VCC = 5 V· LOWPOWER DISSIPATION ICC = 4 mA (MAX.) at TA = 25 °C·HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) ·OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ·SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) ·BALANCEDPROPAGATION DELAYS tPLH = tPHL· WIDE...

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SeekIC No. : 004407149 Detail

M74HC4017: Features: ·HIGH SPEED tPD =21 ns (TYP.) AT VCC = 5 V· LOWPOWER DISSIPATION ICC = 4 mA (MAX.) at TA = 25 °C·HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) ·OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ·...

M74HC4017 Data Sheet

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Part Number:
M74HC4017
Supply Ability:
5000

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  • 1~5000
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  • 15 Days
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Product Details

Description



Features:

·HIGH SPEED
  tPD = 21 ns (TYP.) AT VCC = 5 V
· LOWPOWER DISSIPATION
  ICC = 4 mA (MAX.) at TA = 25 °C
·HIGH NOISE IMMUNITY
  VNIH = VNIL = 28 % VCC (MIN.)
·OUTPUT DRIVE CAPABILITY
  10 LSTTL LOADS
·SYMMETRICAL OUTPUT IMPEDANCE
  |IOH| = IOL = 4 mA (MIN.)
·BALANCEDPROPAGATION DELAYS
  tPLH = tPHL
· WIDE OPERATING VOLTAGE RANGE
  VCC (OPR) = 2 V to 6 V
·PIN AND FUNCTION COMPATIBLEWITH 4017B


Pinout

Connection Diagram


Specifications

Symbol Parameter Value Unit
VCC Supply Voltage -0.5 to +7 V
VI DC Input Voltage -0.5 to VCC + 0.5 V
VO DC Output Voltage -0.5 to VCC + 0.5 V
IIK DC Input Diode Current ± 20 mA
IOK DC Output Diode Current ± 20 mA
IO DC Output Current ± 25 mA
ICC or IGND DC VCC or Ground Current ± 50 mA
PD Power Dissipation 500(*) mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature (10 sec) 300 °C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operationunder these conditions is not implied
(*) 500mW65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C  


Description

The M54/74HC4017 is a high speed CMOS DECADE COUNTER/DIVIDER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption.

The M54/74HC4017 is a 5-stage Johnson counter with 10 decoded outputs. Each of the decoded outputs is normally low and sequentially goes high on the lowto high transition of the clock input.Each output stays high for one clock period of the 10 clock period cycle. The CARRY output goes low to high afterOUTPUT 10 goes low, and can be used in conjunction with the CLOCK ENABLE to cascade several stages.

The CLOCK ENABLE input disables counting when in the high state. A RESET input is also provided which when taken high sets all the decoded outputs low.




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