M74HC40102

The M74HC40102 is an high speed CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTER fabricated with silicon gate C²MOS technology.

The HCF40102 consists of an 8 stage synchronous down counter with a single output which is active when the internal count is zero. The HC40102 is configured as two cascaded 4-bit BCD counters. This device has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT / ZERO DETECT output are active low logic. In normal operation the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN / COUNTER ENABLE (CI/ CE) input is high. The CARRY-OUT / ZERO-DETECT (CO/ZD) output goes low when the count reaches zero if the CI/CE input is low, and remains low for one full clock period. When the SYNCHRONOUS PRESET-ENABLE (SPE) input is low, data at the J input is clocked into the counter on the next positive clock transition regardless of the state of the CI/CE input.

When the ASYNCHRONOUS PRESET-ENABLE (APE) input of M74HC40102 is low, data at the J inputs is asynchronously forced into the counter regardless of the state of the SPE CI/CE or CLOCK inputs. J input J0-J7 represent two 4-bit BCD words. When
the CLEAR, CLR input is low, the counter is asynchronously cleared to its maximum count (9910) regardless of the state of any other input. The precedence relationship between control input is indicated in the truth table. If all control inputs are high at the time of zero count, the counters will jump to the maximum count giving a counting sequence of 100 clock pulses long. The HC40102 may be cascaded using the CI/CE input and the CO/ZD output, in either a synchronous or ripple mode. All inputs are equipped with protection circuits against static discharge and transient excess voltage.