Features: ·HIGH SPEED tPD = 14 ns (TYP.) AT VCC = 5 V ·LOWPOWER DISSIPATION ICC = 1 mA (MAX.) AT TA = 25 °C ·HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) ·OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ·SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) ·BALANCEDPROPAGATION DELAYS tPLH = tPHL ·WI...
M74HC375: Features: ·HIGH SPEED tPD = 14 ns (TYP.) AT VCC = 5 V ·LOWPOWER DISSIPATION ICC = 1 mA (MAX.) AT TA = 25 °C ·HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) ·OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS...
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Symbol | Parameter | Value | Unit |
VCC | Supply Voltage | -0.5 to +7 | V |
VI | DC Input Voltage | -0.5 to VCC + 0.5 | V |
VO | DC Output Voltage | -0.5 to VCC + 0.5 | V |
IIK | DC Input Diode Current | ± 20 | mA |
IOK | DC Output Diode Current | ± 20 | mA |
IO | DC Output Current | ± 25 | mA |
ICC or IGND | DC VCC or Ground Current | ± 50 | mA |
PD | Power Dissipation | 500(*) | mW |
Tstg | Storage Temperature | -65 to +150 | °C |
TL | Lead Temperature (10 sec) | 300 | °C |
The M54/74HC375 is a high speed CMOS QUADD TYPE LATCH fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOSlowpower consumption. It contains two groups of 2-bit latches controlled by an enable input (G1 . 2 orG3 . 4).
The M54/74HC375 can be used in the different circuits. Each latch hasQ and Q outputs (1Q to 4Q and 1Q to 4Q). The data applied to the data input is transferred to the Q and Q outputs when the enable input is taken high and the outputs will follow the data input as long as the enable input is kept high. When the enable input is taken low, the information data applied to the data input at that time is retained at the outputs.
All inputs of The M54/74HC375 are equipped with protection circuits against static discharge and transient excess voltage.