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M74HC368

Features: ·HIGH SPEED: tPD = 9ns (TYP.) at VCC = 6V·LOW POWER DISSIPATION: ICC = 4mA(MAX.) at TA=25°C·HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.)·SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN)·BALANCED PROPAGATION DELAYS: tPLH @ tPHL·WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V...

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SeekIC No. : 004407137 Detail

M74HC368: Features: ·HIGH SPEED: tPD = 9ns (TYP.) at VCC = 6V·LOW POWER DISSIPATION: ICC = 4mA(MAX.) at TA=25°C·HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.)·SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6...

M74HC368 Data Sheet

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Part Number:
M74HC368
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

·HIGH SPEED:
  tPD = 9ns (TYP.) at VCC = 6V
·LOW POWER DISSIPATION:
  ICC = 4mA(MAX.) at TA=25°C
·HIGH NOISE IMMUNITY:
  VNIH = VNIL = 28 % VCC (MIN.)
·SYMMETRICAL OUTPUT IMPEDANCE:
  |IOH| = IOL = 6mA (MIN)
·BALANCED PROPAGATION DELAYS:
  tPLH @ tPHL
·WIDE OPERATING VOLTAGE RANGE:
  VCC (OPR) = 2V to 6V
·PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 368


Pinout

Connection Diagram


Specifications

Symbol Parameter Value Unit
VCC Supply Voltage -0.5 to +7 V
VI
 DC Input Voltage -0.5 to VCC + 0.5 V
VO DC Output Voltage -0.5 to VCC + 0.5 V
IIK DC Input Diode Current ± 20 mA
IOK DC Output Diode Current ± 20 mA
IO DC Output Current ± 35 mA
ICC or IGND DC VCC or Ground Current ± 70 mA
PD Power Dissipation 500(*) mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature (10 sec) 300 °C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operationunder these conditions is not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C




Description

The M74HC368 is an high speed CMOS HEX BUS BUFFER 3-STATE OUTPUTS fabricated with silicon gate C2MOS technology.

M74HC368 contains six buffers, four buffers are controlled by an enable input (G1) and the other two buffers are controlled by the other enable input (G2); the outputs of each buffer group are enabled when G1 and/or G2 inputs are held low, and when held high, these outputs are disabled in a high-impedance state.

All inputs are equipped with protection circuits against static discharge and transient excess voltage.




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