M74HC273

Features: ·HIGH SPEED tPD = 13 ns (TYP.) AT VCC = 5 V· LOWPOWER DISSIPATION ICC = 4 mA (MAX.) at TA = 25 °C·HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) ·OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ·SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) ·BALANCEDPROPAGATION DELAYS tPLH = tPHL· WID...

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M74HC273 Picture
SeekIC No. : 004407119 Detail

M74HC273: Features: ·HIGH SPEED tPD = 13 ns (TYP.) AT VCC = 5 V· LOWPOWER DISSIPATION ICC = 4 mA (MAX.) at TA = 25 °C·HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) ·OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ...

floor Price/Ceiling Price

Part Number:
M74HC273
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

·HIGH SPEED
  tPD = 13 ns (TYP.) AT VCC = 5 V
· LOWPOWER DISSIPATION
  ICC = 4 mA (MAX.) at TA = 25 °C
·HIGH NOISE IMMUNITY
  VNIH = VNIL = 28 % VCC (MIN.)
·OUTPUT DRIVE CAPABILITY
  10 LSTTL LOADS
·SYMMETRICAL OUTPUT IMPEDANCE
  |IOH| = IOL = 4 mA (MIN.)
·BALANCEDPROPAGATION DELAYS
  tPLH = tPHL
·
WIDE OPERATING VOLTAGE RANGE
  VCC (OPR) = 2 V to 6 V
·PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273



Pinout

  Connection Diagram


Specifications

Symbol Parameter Value Unit
VCC Supply Voltage -0.5 to +7 V
VI DC Input Voltage -0.5 to VCC + 0.5 V
VO DC Output Voltage -0.5 to VCC + 0.5 V
IIK DC Input Diode Current ± 20 mA
IOK DC Output Diode Current ± 20 mA
IO DC Output Current ± 25 mA
ICC or IGND DC VCC or Ground Current ± 50 mA
PD Power Dissipation 500(*) mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature (10 sec) 300 °C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operationunder these conditions is not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
  


Description

The M74HC273 is an high speed CMOS OCTAL D TYPE FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology.

Information signals applied to D inputs are transferred to the Q outputs on the positive-going edge of the clock pulse.

When the CLEAR input is held low, the Q output are in the low logic level independent of the other inputs.

All inputs are equipped with protection circuits against static discharge and transient excess voltage.




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