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M74HC251

Features: `HIGH SPEED tPD = 14 ns (TYP.) AT VCC = 5 V `LOWPOWER DISSIPATION ICC = 4 A (MAX.) AT TA = 25 ° C 6 V`OUTPUT DRIVE CAPABILITY10 LSTTL LOADS `SYMMETRICAL OUTPUT IMPEDANCE IOL = |IOH |= 4 mA (MIN.)`HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) `WIDE OPERATING VOLTAGE RANGE VCC (OPR) = ...

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SeekIC No. : 004407112 Detail

M74HC251: Features: `HIGH SPEED tPD = 14 ns (TYP.) AT VCC = 5 V `LOWPOWER DISSIPATION ICC = 4 A (MAX.) AT TA = 25 ° C 6 V`OUTPUT DRIVE CAPABILITY10 LSTTL LOADS `SYMMETRICAL OUTPUT IMPEDANCE IOL = |IOH |= 4 mA...

M74HC251 Data Sheet

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Part Number:
M74HC251
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

`HIGH SPEED tPD = 14 ns (TYP.) AT VCC = 5 V
`LOWPOWER DISSIPATION ICC = 4 A (MAX.) AT TA = 25 ° C  6 V
`OUTPUT DRIVE CAPABILITY   10 LSTTL LOADS
`SYMMETRICAL OUTPUT IMPEDANCE IOL = |IOH |= 4 mA (MIN.)
`HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.)
`WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V
` PIN AND FUNCTION COMPATIBLE WITH 54/74LS251


Pinout

Connection Diagram


Specifications

Symbol
Parameter
Value
Unit
VCC
Supply Voltage
-0.5 to +7
V
VI
DC Input Voltage
-0.5 to VCC + 0.5
V
VO
DC Output Voltage
-0.5 to VCC + 0.5
V
IIK
DC Input Diode Current
± 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Source Sink Current Per Output Pin
± 35
mA
ICC or IGND
DC VCC or Ground Current
± 70
mA
PD
Power Dissipation
500 (*)
mW
Tstg
Storage Temperature
-65 to +150
°C
TL
Lead Temperature (10 sec)
300
°C
AbsoluteMaximumRatings are those values beyond whichdamage tothe device may occur. Functional operation under these condition isnotimplied.(*) 500 mW:  65 °C derate to 300mWby 10mW/°C: 65 °C to85°C


Description

The M54/74HC251 is a high speed CMOS8-CHANNELMULTIPLEXER  (3-STATE) fabricated insilicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This multiplexer features both true (Y) and complement (W) outputs as well as STROBE input. The STROBE must be a low logic level to enable this device. When theSTROBE input is high, both outputs are in the high impedance state. When enabled, address information on the data select inputs determines which data input is routed to Y and W. All inputs are equipped with protection circuits against static discharge and transient excess voltage.




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