Features: HIGH SPEED tPD = 12 ns (TYP.)at VCC = 5VLOWPOWER DISSIPATION ICC = 4 A (MAX.)AT TA = 25 °C 6 VHIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADSSYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCEDPROPAGATION DELAYS tPLH = tPHL WIDE OPERATING...
M74HC237: Features: HIGH SPEED tPD = 12 ns (TYP.)at VCC = 5VLOWPOWER DISSIPATION ICC = 4 A (MAX.)AT TA = 25 °C 6 VHIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADSSYMMET...
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Symbol |
Parameter |
Value |
Unit |
VCC |
Supply Voltage |
-0.5 to +7 |
V |
VI |
DC Input Voltage |
-0.5 to VCC + 0.5 |
V |
VO |
DC Output Voltage |
-0.5 to VCC + 0.5 |
V |
IIK |
DC Input Diode Current |
± 20 |
mA |
IOK |
DC Output Diode Current |
± 20 |
mA |
IO |
DC Output Source Sink Current Per Output Pin |
± 25 |
mA |
ICC or IGND |
DC VCC or Ground Current |
± 50 |
mA |
PD |
Power Dissipation |
500 (*) |
mW |
Tstg |
Storage Temperature |
-65 to +150 |
°C |
TL |
Lead Temperature (10 sec) |
300 |
°C |
The M54/74HC237 is a high speed CMOS 3 TO 8 LINE DECODER LATCH fabricated in silicon gate C2MOStechnology.
The M54/74HC237 has the same high speed performance of LSTTL combined with true CMOS low power consumption. When GL goes from low to high, the address present at the select inputs (A, B, C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable controls, G1 and G2 control the state of the outputs independantly of the select or latch-enable inputs. All of the outputs are low unlessG1 is high and G2 is low. The 'HC237 is ideally suited for the implementation of glitch-free decoders in stored-address applications in bus oriented systems. All inputs are equipped with protection circuits against static discharge and transient excess voltage.