M58WR128ET

Features:

`SUPPLY VOLTAGE
          VDD = 1.65V to 2.2V for Program, Erase and Read
          VDDQ = 1.65V to 3.3V for I/O Buffers
          VPP = 12V for fast Program (optional)
`SYNCHRONOUS / ASYNCHRONOUS READ
          Synchronous Burst Read mode: 54MHz
          Asynchronous/ Synchronous Page Read mode
          Random Access: 70, 80, 100ns
`SYNCHRONOUS BURST READ SUSPEND
`PROGRAMMING TIME
          8µs by Word typical for Fast Factory Program
          Double/Quadruple Word Program option
          Enhanced Factory Program options
`MEMORY BLOCKS
          Multiple Bank Memory Array: 4 Mbit Banks
          Parameter Blocks (Top or Bottom location)
`DUAL OPERATIONS
          Program Erase in one Bank while Read in others
          No delay between Read and Write operations
`BLOCK LOCKING
          All blocks locked at Power up
          Any combination of blocks can be locked
          WP for Block Lock-Down
`SECURITY
          128 bit user programmable OTP cells
          64 bit unique device number
          One parameter block permanently lockable
`COMMON FLASH INTERFACE (CFI)
`100,000 PROGRAM/ERASE CYCLES per BLOCK
`ELECTRONIC SIGNATURE
          Manufacturer Code: 20h
          Top Device Code, M58WR128ET: 881Eh
          Bottom Device Code, M58WR128EB: 881Fh


Specifications

		Value
Symbol	Parameter	Min	Max	Unit
TA	Ambient Operating Temperature	40	85
TBIAS	Temperature Under Bias	40	125
TSTG	Storage Temperature	65	155
VIO	Input or Output Voltage	0.5	VDDQ+0.6	V
VDD	Supply Voltage	0.2	2.45	V
VDDQ	Input/Output Supply Voltage	0.2	3.6	V
VPP	Program Voltage	0.2	14	V
IO	Output Short Circuit Current		100	mA
tVPPH	Time for VPP at VPPH		100	hours

Description

The M58WR128E is a 128 Mbit (8Mbit x16) nonvolatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.65V to 2.2V VDD supply for the circuitry and a 1.65V to 3.3V VDDQ supply for the Input/Output pins. An optional 12V VPP power supply is provided to speed up customer programming.

The device M58WR128E features an asymmetrical block architecture. M58WR128E has an array of 263 blocks, and is divided into 4 Mbit banks. There are 31 banks each containing 8 main blocks of 32 KWords, and one parameter bank containing 8 parameter blocks of 4 KWords and 7 main blocks of 32 KWords. The Multiple Bank Architecture allows Dual Operations, while programming or erasing in one bank, Read operations are possible in other banks. Only one bank at a time is allowed to be in Program or Erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory maps are shown in Figure 4. The Parameter Blocks are located at the top of the memory address space for the M58WR128ET, and at the bottom for the M58WR128EB.

Each block M58WR128E can be erased separately. Erase can be suspended, in order to perform program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage VDD. There are two Enhanced Factory programming commands available to speed up programming.

M58WR128E Program and Erase commands are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst mode, data is output on each clock cycle at frequencies of up to 54MHz. The synchronous burst read operation can be suspended and resumed.

The device M58WR128E features an Automatic Standby mode. When the bus is inactive during Asynchronous Read operations, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value IDD4 and the outputs are still driven.

The M58WR128E features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are locked at Power-Up.

The device M58WR128E includes a Protection Register and a Security Block to increase the protection of a system's design. The Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by ST, and a 128 bit segment One-Time-Programmable (OTP) by the user. The user programmable segment can be permanently protected. The Security Block, parameter block 0, can be permanently protected by the user. Figure 5, shows the Security Block and Protection Register Memory Map.
The M58WR128E memory is available in a VFBGA60 12.5x12mm package and is supplied with all the bits erased (set to '1').