M58LR128KD

Supply voltage
V_DD = 1.7 V to 2.0 V for program, erase and read
V_DDQ = 1.7 V to 2.0 V for I/O buffers
V_PP = 9 V for fast program
Multiplexed address/data
Synchronous/asynchronous read
Synchronous burst read mode:
66 MHz, 86 MHz
Random access: 70 ns
Synchronous burst read suspend
Programming time
2.5 s typical word program time using Buffer Enhanced Factory Program command
Memory organization
Multiple bank memory array:
8 Mbit banks for the M58LR128KC/D
16 Mbit banks for the M58LR256KC/D
Parameter blocks (top or bottom location)
Dual operations
Program/erase in one bank while read in others
No delay between read and write operations
Common Flash interface (CFI)
100 000 program/erase cycles per block
Block locking
All blocks locked at power-up
Any combination of blocks can be locked with zero latency
 WP for block lock-down
Absolute write protection with VPP = VSS
Security
64 bit unique device number
2112 bit user programmable OTP Cells
Electronic signature
Manufacturer code: 20h
Top device codes:
M58LR128KC: 882Eh
M58LR256KC: 881Ch
Bottom device codes
M58LR128KD: 882Fh
M58LR256KD: 881Dh

The M58LR128KC/D and M58LR256KC/D are 128 Mbit (8 Mbit *16) and 256 Mbit (16 Mbit *16) non-volatile Flash memories, respectively. They may be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.7 V to 2.0 V V_DD supply for the circuitry and a 1.7 V to 2.0 V V_DDQ supply for the input/output pins. An optional 9 V V_PP power supply is provided to speed up factory programming. In the rest of the document they are collectively referred to as the M58LRxxxKC/D unless otherwise specified.

The M58LR128KC/D and M58LR256KC/D first sixteen address lines are multiplexed with the data input/output signals on the multiplexed address/data bus ADQ0-ADQ15. The remaining address lines A16-Amax are the most significant bit addresses.

The M58LR128KC/D and M58LR256KC/D devices feature an asymmetrical block architecture:
The M58LR128KC/D has an array of 131 blocks, and are divided into 8 Mbit banks.There are 15 banks each containing 8 main blocks of 64 KWords, and one parameter bank containing 4 parameter blocks of 16 KWords and 7 main blocks of 64 KWords.
The M58LR256KC/D has an array of 259 blocks, and is divided into 16 Mbit banks.There are 15 banks each containing 16 main blocks of 64 KWords, and one parameter bank containing 4 parameter blocks of 16 KWords and 15 main blocks of 64 KWords.

The M58LR128KC/D and M58LR256KC/D multiple bank architecture allows dual operations; while programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries.

The M58LR128KC/D and M58LR256KC/D bank architectures are summarized in Table 2 and Table 3 and the memory maps are shown in Figure 2 and Figure 3. The parameter blocks are located at the top of the memory address space for the M58LR128KC and M58LR256KC, and at the bottom for the M58LR128KD and M58LR256KD.

Each block M58LR128KC/D and M58LR256KC/D can be erased separately. Erase can be suspended to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed.

Each block M58LR128KC/D and M58LR256KC/D can be programmed and erased over 100 000 cycles using the supply voltage VDD. There is a Buffer Enhanced Factory Programming command available to speed up programming.

M58LR128KC/D and M58LR256KC/D Program and erase commands are written to the command interface of the memory. An internal Program/Erase Controller manages the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards.

The device M58LR128KC/D and M58LR256KC/D supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst read mode, data is output on each clock cycle at frequencies of up to 86 MHz. The synchronous burst read operation can be suspended and resumed.

The device M58LR128KC/D and M58LR256KC/D features an automatic standby mode. When the bus is inactive during asynchronous read operations, the device automatically switches to the automatic standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven.