M58LR128KB

The M58LR128KT/B and M58LR256KT/B are 128 Mbit (8 Mbit *16) and 256 Mbit (16 Mbit *16) non-volatile Flash memories, respectively. They can be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.7 V to 2.0 V V_DD supply for the circuitry and a 1.7 V to 2.0 V V_DDQ supply for the input/output pins. An optional 9 V V_PP power supply is provided to accelerate factory programming.

The devices M58LR128KT/B feature an asymmetrical block architecture:
The M58LR128KT/B have an array of 131 blocks, and are divided into 8 Mbit banks. There are 15 banks each containing 8 main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16 Kwords and 7 main blocks of 64 Kwords.
The M58LR256KT/B have an array of 259 blocks, and are divided into 16 Mbit banks.
There are 15 banks each containing 16 main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16 Kwords and 15 main blocks of 64 Kwords.

The M58LR128KT/B multiple bank architecture allows dual operations. While programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries.

The M58LR128KT/B bank architecture is summarized in Table 2, and the memory map is shown in Figure 2.

The parameter blocks are located at the top of the memory address space for the M58LR128KT and M58LR256KT, and at the bottom for the M58LR128KB and M58LR256KB.

Each block M58LR128KT/B can be erased separately. Erase can be suspended to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed.

Each block M58LR128KT/B can be programmed and erased over 100 000 cycles using the supply voltage VDD. There is a buffer enhanced factory programming command available to speed up programming.

Program and erase commands are written to the command interface of the memory. An internal Program/Erase Controller manages the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards.

The device M58LR128KT/B supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst read mode, data is output on each clock cycle at frequencies of up to 66 MHz. The synchronous burst read operation can be suspended and resumed.

The device M58LR128KT/B features an automatic standby mode. When the bus is inactive during asynchronous read operations, the device automatically switches to automatic standby ode. In this condition the power consumption is reduced to the standby value and the outputs are still driven.

The M58LRxxxKT/B features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When V_PP V_PPLK all blocks are protected against program or erase. All blocks are locked at power-up.