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M366S3253CTS

Features: • Performance range• Burst mode operation• Auto & self refresh capability (8192 Cycles/64ms)• LVTTL compatible inputs and outputs• Single 3.3V ± 0.3V power supply• MRS cycle with address key programs Latency (Access from column address) Burst lengt...

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SeekIC No. : 004404814 Detail

M366S3253CTS: Features: • Performance range• Burst mode operation• Auto & self refresh capability (8192 Cycles/64ms)• LVTTL compatible inputs and outputs• Single 3.3V ± 0.3V powe...

M366S3253CTS Data Sheet

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Part Number:
M366S3253CTS
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/27

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Product Details

Description



Features:

• Performance range
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Serial presence detect with EEPROM
• PCB : Height (1,375mil), single sided component


Specifications

Parameter
Symbol
Value
Units
Voltage on any pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD pin relative to VSS
VDD,VDDQ
-1.0 ~ 4.6
V
Storage Temperature
TSTG
-55 to ~150
°C
Power dissipation
PD
8
W
Short circuit current
IOS
50
mA



Description

The Samsung M366S3253CTS is a 32M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M366S3253CTS consists of eight CMOS 32M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate.  Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M366S3253CTS is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets.

Synchronous M366S3253CTS design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies M366S3253CTS allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.




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