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M2S12D20TP

Features: · Vdd=Vddq=2.5V ± 0.2V· Double data rate architecture; two data transfers per clock cycle· Bidirectional, data strobe (DQS) is transmitted/received with data· Differential clock inputs (CLK and /CLK)· DLL aligns DQ and DQS transitions· Commands are entered on each positive CLK edge;· dat...

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SeekIC No. : 004404475 Detail

M2S12D20TP: Features: · Vdd=Vddq=2.5V ± 0.2V· Double data rate architecture; two data transfers per clock cycle· Bidirectional, data strobe (DQS) is transmitted/received with data· Differential clock inputs (CL...

M2S12D20TP Data Sheet

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Part Number:
M2S12D20TP
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· Vdd=Vddq=2.5V  ± 0.2V
· Double data rate architecture; two data transfers per clock cycle
· Bidirectional, data strobe (DQS) is transmitted/received with data
· Differential clock inputs (CLK and /CLK)
· DLL aligns DQ and DQS transitions
· Commands are entered on each positive CLK edge;
· data and data mask are referenced to both edges of DQS
· 4 bank operations are controlled by BA0, BA1 (Bank Address)
· /CAS latency- 2.0/2.5 (programmable)
· Burst length- 2/4/8 (programmable)
· Burst type- sequential / interleave (programmable)
· Auto precharge / All bank precharge is controlled by A10
· 8192 refresh cycles /64ms (4 banks concurrent refresh)
· Auto refresh and Self refresh
· Row address A0-12 / Column address A0-9,11-12(x4)/ A0-9,11(x8) SSTL_2 Interface
· 400-mil, 66-pin Thin Small Outline Package (TSOP II)
· JEDEC standard
· Low Power for the Self Refresh Current ICC6 :4mA (-75L,-10L)


Specifications



Symbol
Parameter
Conditions
Ratings
Unit
Vdd Supply Voltage
with respect to Vss
-0.5 ~ 3.7
V
VddQ Supply Voltage for Output
with respect to VssQ
-0.5 ~ 3.7
V
VI Input Voltage
with respect to Vss
-0.5 ~ Vdd+0.5
V
VO Output Voltage
with respect to VssQ
-0.5~ VddQ+0.5
V
IO Output Current
50
mA
Pd Power Dissipation
Ta = 25
1000
mW
Topr Operating Temperature
0 ~ 70
Tstg Storage Temperature
-65 ~ 150





Description

M2S12D20TP is a 4-bank x 33,554,432-word x 4-bit, M2S12D30TP is a 4-bank x 16,777,216-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobes, and output data and data strobe are referenced on both edges of CLK. The M2S12D20TP achieve very high speed data rate up to 133MHz, and are suitable for main memory in computer systems.




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