M29W320DT

Features:

SUPPLY VOLTAGE
   V_CC = 2.7V to 3.6V for Program, Erase and Read
   VPP =12V for Fast Program (optional)
ACCESS TIME: 70, 90ns
PROGRAMMING TIME
   10µs per Byte/Word typical
67 MEMORY BLOCKS
   1 Boot Block (Top or Bottom Location)
   2 Parameter and 64 Main Blocks
PROGRAM/ERASE CONTROLLER
   Embedded Byte/Word Program algorithms
ERASE SUSPEND and RESUME MODES
   Read and Program another Block during Erase Suspend
UNLOCK BYPASS PROGRAM COMMAND
   Faster Production/Batch Programming
VPP/WP PIN for FAST PROGRAM and WRITE PROTECT
TEMPORARY BLOCK UNPROTECTION MODE
COMMON FLASH INTERFACE
   64 bit Security Code
LOW POWER CONSUMPTION
   Standby and Automatic Standby
100,000 PROGRAM/ERASE CYCLES per BLOCK
ELECTRONIC SIGNATURE
   Manufacturer Code: 0020h
   Top Device Code M29W320DT: 22CAh
   Bottom Device Code M29W320DB: 22CBh


Pinout




Specifications

Symbol	Parameter	Min	Max	Unit
TBIAS	Temperature Under Bias	50	125	°C
TSTG	Storage Temperature	65	150	°C
VIO	Input or Output Voltage (1,2)	0.6	VCC +0.6	V
VCC	Supply Voltage	0.6	4	V
VID	Identification Voltage	0.6	13.5	V
VPP	Program Voltage	0.6	13.5	V

Description

The M29W320DT is a 32 Mbit (4Mb x8 or 2Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM.

The memory M29W320DT is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation M29W320DT can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.