M29W102BT

Features:

SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS
ACCESS TIME: 50ns
PROGRAMMING TIME
10s per Word typical
5 MEMORY BLOCKS
1 Boot Block (Top or Bottom Location)
2 Parameter and 2 Main Blocks
PROGRAM/ERASE CONTROLLER
Embedded Word Program algorithm
Embedded Multi-Block/Chip Erase algorithm
Status Register Polling and Toggle Bits
ERASE SUSPEND and RESUME MODES
Read and Program another Block during Erase Suspend
UNLOCK BYPASS PROGRAM COMMAND
Faster Production/Batch Programming
TEMPORARY BLOCK UNPROTECTION MODE
LOW POWER CONSUMPTION
Standby and Automatic Standby
100,000 PROGRAM/ERASE CYCLES per BLOCK
M28F102 COMPATIBLE
Pin-out and Read Mode
20 YEARS DATA RETENTION
Defectivity below 1 ppm/year
ELECTRONIC SIGNATURE
Manufacturer Code: 0020h
Top Device Code M29W102BT: 0099h
Bottom Device Code M29W102BB: 0098h


Pinout




Specifications

Symbol	Parameter	Value	Unit
TA	Ambient Operating Temperature (Temperature Range Option 1)	0 to 70
	Ambient Operating Temperature (Temperature Range Option 6)	-40 to 85
TBIAS	Temperature Under Bias	-50 to 125
TSTG	Storage Temperature	65 to 150
VIO(2)	Input or Output Voltage	0.6 to 4	V
VCC	Supply Voltage	0.6 to 4	V
VID	Identification Voltage	0.6 to 13.5	V

Description

The M29W102BT is a 1 Mbit (64Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM.

The memory M29W102BT is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

The blocks in the memory M29W102BT are asymmetrically arranged, see Tables 3 and 4, Block Addresses. The first or last 32 Kwords have been divided into four additional blocks. The 8 Kword Boot Block can be used for small initialization code to start the microprocessor, the two 4 Kword Parameter Blocks can be used for parameter storage and the remaining 16 Kwords are a small Main Block where the application may be stored.

Chip Enable, Output Enable and Write Enable signals M29W102BT control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic.

The memory M29W102BT is offered in a TSOP40 (10 x 14mm) package and it is supplied with all the bits erased (set to '1').