M25PE80VMP6G

The M25PE80VMP6G belongs to M25PE80 family. All instructions, addresses and data are shifted in and out of the device, most significant bit first. The instruction set is listed in Table 6. Every instruction sequence starts with a one-Byte instruction code. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-Byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C). Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Write (PW), Page Program (PP), Write to Lock Register (WRLR), Page Erase (PE), Sector Erase (SE), Bulk Erase (BE), Write Enable (WREN), Write Disable (WRDI), Deep Power-down (DP) or Release from Deep Power- down (RDP) instruction, Chip Select (S) must be driven High exactly at a Byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven high when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write cycle, Program cycle or Erase cycle are ig- nored, and the internal Write cycle, Program cycle or Erase cycle continues unaffected. Depending on the instruction, this might be followed by address Bytes, or by data Bytes, or by both or none. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read Identification (RDID), Read Status Register (RD- SR) M25PE80VMP6G, or Read Lock Register (RDLR) instruction, the shifted-in instruction sequence is followed by a data-out sequence.

The features of M25PE80VMP6G can be summarized as (1)industrial standard SPI pin-out; (2)8 Mbits of page-erasable flash memory; (3)page write (up to 256 Bytes) in 11ms (typical); (4)page program (up to 256 Bytes) in 1.2ms (typical); (5)page erase (256 Bytes) in 10ms (typical); (6)sector erase (512 Kbits); (7)bulk erase (8 Mbits); (8)2.7 to 3.6V single supply voltage; (9)SPI bus compatible serial interface; (10)50MHz clock rate (maximum); (11)deep power-down mode 1A (typical); (12)electronic signature JEDEC standard two-byte signature (8014h); (13)more than 100,000 write cycles; (14)more than 20 year data retention; (15)hardware write protection of the top sector (64KB); (16)software write protection on a 64KByte sector basis; (17)software write protection on a 4KByte sub-sector basis for sector 0 and sector 15.

The absolute maximum ratings of M25PE80VMP6G are (1)TSTG storage temperature: -65 to 150 °C; (2)T LEAD lead temperature during soldering: see note 1 °C; (3)V IO input and output voltage (with respect to ground): -0.6 to 4.0 V; (4)VCC supply voltage: -0.6 to 4.0 V; (5)VESD electrostatic discharge voltage (human body model):2: -2000 to 2000 V(Note: 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK? 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500, R2=500)).