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M12L16161A

Features: · JEDEC standard 3.3V power supply · LVTTL compatible with multiplexed address · Dual banks operation · MRS cycle with address key programs - CAS Latency (2 & 3 ) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) · All inputs are sampled at the p...

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SeekIC No. : 004403920 Detail

M12L16161A: Features: · JEDEC standard 3.3V power supply · LVTTL compatible with multiplexed address · Dual banks operation · MRS cycle with address key programs - CAS Latency (2 & 3 ) - Burst Length (1, 2...

M12L16161A Data Sheet

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Part Number:
M12L16161A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

  · JEDEC standard 3.3V power supply
  · LVTTL compatible with multiplexed address
  · Dual banks operation
  · MRS cycle with address key programs
     - CAS Latency (2 & 3 )
     - Burst Length (1, 2, 4, 8 & full page)
     - Burst Type (Sequential & Interleave)
  · All inputs are sampled at the positive going edge of the system clock
  · Burst Read Single-bit Write operation
  · DQM for masking
  · Auto & self refresh
  · 32ms refresh period (2K cycle)


Pinout

Connection Diagram


Specifications

Parameter

Symbol

Value

Unit

Voltage on any pin relative to VSS

VIN,VOUT

-1.0 ~ 4.6

V

Voltage on VDD supply relative to VSS

VDD,VDDQ

-1.0 ~ 4.6

V

Storage temperature

TSTG

-55 ~ + 150

Power dissipation

PD

1

W

Short circuit current

IOS

50

MA

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.




Description

The M12L16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.




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