M12L128168A

The M12L128168A has the following features including JEDEC standard 3.3V power supply;LVTTL compatible with multiplexed address;Four banks operation;MRS cycle with address key programs:-CAS Latency(2&3),Burst Length(1,2, 4, 8&full page),Burst Type(Sequential&Interleave);All inputs are sampled at the positive going edge of the system clock;Burst Read single write operation;DQM for masking;Auto&self refresh;64ms refresh period(4K cycle).

The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

The M12L128168A clock enable (CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down  exit  is synchronous  as the  internal  clock  is suspended. When CKE goes high at least "1CLK+t55" before the high going edge of the clock, then the SDRAM becomes active from  the same  clock edge accepting  all  the  input commands.