Features: `25 ns Worst-Case Multiply Time
`Low Power CMOS Technology
`Replaces Cypress CY7C517, IDT 7217L, and AMD Am29517
`Single Clock Architecture with Register Enables
`Two's Complement, Unsigned, or Mixed Operands
`Three-State Outputs
`68-pin PLCC, J-Lead
SpecificationsStorage temperature ........................................................................................................... 65 to +150
Operating ambient temperature .......................................................................................... 55 to +125
VCC supply voltage with respect to ground ......................................................................... 0.5 V to +7.0 V
Input signal with respect to ground ..................................................................................... 3.0 V to +7.0 V
Signal applied to high impedance output .............................................................................. 3.0 V to +7.0 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ................................................................................................................................. > 400 mADescriptionThe LMU217 is a high-speed, low power 16-bit parallel multiplier.
The LMU217 produces the 32-bit product of two 16-bit numbers. Data present at the A inputs, along with the TCA control bit, is loaded into the A register on the rising edge of CLK. B data and the TCB control bit are similarly loaded. Loading of the A and B registers is controlled by the ENA and ENB controls. When HIGH, these controls prevent application of the clock to the respective register.
The TCA and TCB controls specify the operands as two's complement when HIGH, or unsigned magnitude when LOW. RND is loaded on the rising edge of CLK, provided either ENA or ENB are LOW. RND, when HIGH, adds '1' to the most significant bit position of the least significant half of the product. Subsequent truncation of the 16 least significant bits produces a result correctly rounded to 16-bit precision. At the output, the Right Shift control (RS) selects either of two output formats. RS LOW produces a 31-bit product with a copy of the sign bit inserted in the MSB postion of the least significant half. RS HIGH gives a full 32-bit product. Two 16-bit output registers are provided to hold the most and least significant halves of the result (MSP and LSP) as defined by RS. These registers are loaded on the rising edge of CLK, subject to the ENR control. When ENR is HIGH, clocking of the result registers is prevented.
For asynchronous output, these registers may be made transparent by setting the feed through control (FT) HIGH and ENR LOW.
The two halves of the product may be routed to a single 16-bit three-state output port (MSP) via a multiplexer. MSPSEL LOW causes the MSP outputs to be driven by the most significant half of the result. MSPSEL HIGH routes the least significant half of the result to the MSP pins. In addition, the LSP is available via the B port through a separate three-state buffer.
LMU217 Data Sheet
