LMU216

The LMU16 and LMU216 are highspeed, low power 16-bit parallel multipliers. The LMU16 and LMU216 are functionally identical; they differ only in packaging.

The LMU16 and LMU216 produce the 32-bit product of two 16-bit numbers. Data present at the A inputs, along with the TCA control bit, is loaded into the A register on the rising edge of CLK A. B data and the TCB control bit are similarly loaded by CLK B.

The TCA and TCB controls specify the A and B operands as two's complement when HIGH, or unsigned magnitude when LOW. RND is loaded on the rising edge of the logical OR of CLK A and CLK B. RND, when HIGH, adds '1' to the most significant bit position of the least significant half of the product. Subsequent truncation of the 16 least significant bits produces a result correctly rounded to 16-bit precision. At the output, the Right Shift control (RS) selects either of two output formats. RS LOW produces a 31-bit product with a copy of the sign bit inserted in the MSB postion of the least significant half. RS HIGH gives a full 32-bit product. Two 16-bit output registers are provided to hold the most and least significant halves of the result (MSP and LSP) as defined by RS. These registers are loaded on the rising edge of CLK M and CLK L respectively. For asynchronous output, these registers may be made transparent by setting the feed through control (FT) HIGH.

The two halves of the LMU216 may be routed to a single 16-bit three-state output port (MSP) via a multiplexer. MSPSEL LOW causes the MSP outputs to be driven by the most significant half of the result. MSPSEL HIGH routes the least significant half of the result to the MSP outputs. In addition, the LSP is available via the B port through a separate three-state buffer.

The output multiplexer control MSPSEL uses a pin which is a supply ground in the Fairchild MPY016H/ TMC216H. When this control is LOW (GND), the function is that of the MPY016H/TMC216H, thus allowing full compatibility.