PinoutSpecificationsFunctionReceiverBits18 or 24Max PCLK Frequency30 MHzVDDP1.6V to 2.0VVDDI/O1.6V to 2.0VTarget ApplicationMobile PhoneRecommended InterfaceRGBSelectable Edge RateYesPowerWise TechnologyMobile Pixel Link BridgeExternal Filters Req'dNoI/O LevelsMPL-2Special FeaturesAuto Power Down ...
LM4310: PinoutSpecificationsFunctionReceiverBits18 or 24Max PCLK Frequency30 MHzVDDP1.6V to 2.0VVDDI/O1.6V to 2.0VTarget ApplicationMobile PhoneRecommended InterfaceRGBSelectable Edge RateYesPowerWise Techn...
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Function | Receiver |
Bits | 18 or 24 |
Max PCLK Frequency | 30 MHz |
VDDP | 1.6V to 2.0V |
VDDI/O | 1.6V to 2.0V |
Target Application | Mobile Phone |
Recommended Interface | RGB |
Selectable Edge Rate | Yes |
PowerWise Technology | Mobile Pixel Link Bridge |
External Filters Req'd | No |
I/O Levels | MPL-2 |
Special Features | Auto Power Down on Stop Clock , SPI Interface |
ESD | 2 kV |
View Using Catalog |
The LM4310 deserializes a Two Data + Clock Mobile Pixel Link (MPL-2) RGB serial link. Two operating modes are supported: 24-bit RGB and also 18-bit RGB.
The video interconnect is reduced from 28 signals to 3 differential signals with the LM4312 SER and companion LM4310 DES device, easing flex interconnect design, size constraints and cost.
Bufferless displays from QVGA (320 x 240) up to >VGA (640 x 480) pixels are supported.
The Deserializer also provides a glitch filter on the three control signals (DE, VS and HS). Glitches of 1 or 2 PCLKs wide are filtered out by the Deserializer to prevent flicker on the display.
Performance of the serial link can be checked by use of the parity/packet error reporting pin that monitors the serial payload odd parity bit and reports errors.
The LM4310 DES and LM4312 SER implements the physical layer of the MPL-2 Interface and features robust common-mode noise rejection.