LF2247

The LF2247 consists of an array of four 11 x 10-bit registered multipliers followed by a summer and a 25-bit accumulator.  The LF2247 provides a coefficient register file containing four 32 x 11-bit registers which are capable of storing 32 different sets of filter coefficients for the multiplier array.

All multiplier data inputs are user accessible and can be updated every clock cycle with either fractional or integer two's complement data.  The pipelined architecture has fully registered input and output ports and an asynchronous three-state output enable control to simplify the design of complex systems.  The pipeline latency for all inputs is five clock cycles.

A 25-bit accumulator path allows cumulative word growth which may be internally rounded to 16 bits.

Output data is updated every clock cycle and may be held under user control.  The data inputs/outputs and control inputs are registered on the rising edge of CLK.  The Serial Data In signal, SDIN, is registered on the rising edge of SCLK.  The LF2247 operates at a clock rate of 66 MHz over the full temperature and supply voltage ranges.

The LF2247 is applicable for perform- ing pixel interpolation in image manipulation and filtering applica- tions.  The LF2247 can perform a bilinear interpolation of an image (4- pixel kernels) at real-time video rates when used with an image resampling sequencer.  Larger kernels or more complex functions can be realized by utilizing multiple devices.

Unrestricted access to all data ports and an addressable coefficient register file provides the LF2247 with consid- erable flexibility in applications such as digital filters, adaptive FIR filters,mixers, and other similar systems requiring high-speed processing.