LF2246

The LF2246 consists of an array of four 11 x 10-bit registered multipliers followed by a summer and a 25-bit accumulator.  All multiplier inputs are user accessible and can be up- dated every clock cycle with either fractional or integer two's comple- ment data.  The pipelined architecture has fully registered input and output ports and an asynchronous three-state output enable control to simplify the design of complex systems.  The pipeline latency for all inputs is five clock cycles.

Storage for mixing and filtering coefficients can be accomplished by holding the data or coefficient inputs over multiple clock cycles.  A 25-bit accumulator path allows cumulative word growth which may be internally rounded to 16 bits.  Output data is updated every clock cycle and may be held under user control.  All inputs, outputs, and controls are registered on the rising edge of clock, except for OEN.  The LF2246 operates at a clock rate of 66 MHz over the full tempera- ture and supply voltage ranges.

The LF2246 is applicable for perform- ing pixel interpolation in image manipulation and filtering applica- tions.  The LF2246 can perform a bilinear interpolation of an image (4- pixel kernels) at real-time video rates when used with an image resampling sequencer.  Larger kernels or more complex functions can be realized by utilizing multiple devices.

Unrestricted access to all data and coefficient input ports provides the LF2246 with considerable flexibility in applications such as digital filters,adaptive FIR filters, mixers, and other similar systems requiring high-speed processing.