Features: `Architecture• Design Technology: 0.12m• Voltage Supply- 1.8V device(KFM1216Q2M) : 1.7V~1.95V• Organization- Host Interface:16bit• Internal BufferRAM(5K Bytes)- 1KB for BootRAM, 4KB for DataRAM• NAND Array- Page Size : (2K+64)bytes- Block Size : (128K+4K)byt...
KFM1216Q2M: Features: `Architecture• Design Technology: 0.12m• Voltage Supply- 1.8V device(KFM1216Q2M) : 1.7V~1.95V• Organization- Host Interface:16bit• Internal BufferRAM(5K Bytes)- 1KB...
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Features: `Device Architecture• Design Technology:..............90nm• Supply Voltage:....
`Architecture
• Design Technology: 0.12m
• Voltage Supply
- 1.8V device(KFM1216Q2M) : 1.7V~1.95V
• Organization
- Host Interface:16bit
• Internal BufferRAM(5K Bytes)
- 1KB for BootRAM, 4KB for DataRAM
• NAND Array
- Page Size : (2K+64)bytes
- Block Size : (128K+4K)bytes
`Performance
• Host Interface type
- Synchronous Burst Read
: Clock Frequency: up to 54MHz(1.8V device)
: Linear Burst - 4 , 8 , 16 words with wrap-around
: Continuous Sequential Burst(1K words)
- Asynchronous Random Read
: Access time of 76ns
- Asynchronous Random Write
• Programmable Read latency
• Multiple Sector Read
- Read multiple sectors by Sector Count Register(up to 4 sectors)
• Reset Mode
- Cold Reset / Warm Reset / Hot Reset / NAND Flash Reset
• Power dissipation (typical values)
- Standby current : 10uA
- Asynchronous Read current : 8mA
- Synchronous Burst Read current(54MHz) : 12mA
- Load current : 20mA
- Program current: 20mA
- Erase current: 15mA
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
`Hardware Features
• Voltage detector generating internal reset signal from Vcc
• Hardware reset input (RP)
• Data Protection
- Write Protection mode for BootRAM
- Write Protection mode for NAND Flash Array
- Write protection during power-up
- Write protection during power-down
• User-controlled One Time Programmable(OTP) area
• Internal 2bit EDC / 1bit ECC
• Internal Bootloader supports Booting Solution in system
`Software Features
• Handshaking Feature
- INT pin: Indicates Ready / Busy of MuxOneNAND
- Polling method: Provides a software method of detecting the Ready / Busy status of MuxOneNAND
• Detailed chip information by ID register
`Packaging
• Package
- 48ball, 12mm x 9.5mm x max 1.0mmt , 0.5mm ball pitch FBGA
Parameter |
Symbol |
Rating |
Unit | |
Voltage on any pin relative to VSS | Vcc |
Vcc |
-0.5 to + 2.45 |
V |
All Pins |
VIN |
-0.5 to + 2.45 | ||
Temperature Under Bias | Extended |
Tbias |
-30 to +125 |
|
Storage Temperature |
Tstg |
-65 to +150 |
||
Short Circuit Output Current |
IOS |
5 |
mA | |
Operating Temperature | Extended |
TA |
-30 to + 85 |
MuxOneNAND is a single-die chip with Muxed NOR Flash interface using NAND Flash Array. This device is comprised of logic and NAND Flash Array and 5KB internal BufferRAM. 1KB BootRAM is used for reserving bootcode, and 4KB DataRAM is used for buffering data. The operating clock frequency is up to 54MHz(1.8V device). This device is X16 interface with Host, and has the speed of ~76ns random access time. Actually, it is accessible with minimum 4clock latency(host-driven clock for synchronous read), but this device adopts the appropriate wait cycles by programmable read latency. MuxOneNAND provides the multiple sector read operation by assigning the number of sectors to be read in the sector counter register. The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide identification capabilities.