Features: • 1.8V+0.1V/-0.1V Power Supply.
• DLL circuitry for wide output data valid window and future freguency scaling.
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,1.8V+0.1V/-0.1V for 1.8V I/O.
• Pipelined, double-data rate operation.
• Common data input/output bus .
• HSTL I/O
• Full data coherency, providing most current data.
• Synchronous pipeline read with self timed late write.
• Registered address, control and data input/output.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 2-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks(K and K) for accurate DDR timing at clock rising edges only.
• Two input clocks for output data(C and C) to minimize clock-skew and flight-time mismatches.
• Two echo clocks (CQ and CQ) to enhance output data traceability.
• Single address bus.
• Byte write (x18, x36) function.
• Simple depth expansion with no data contention.
• Programmable output impedance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball array FBGA) with body size of 13x15mm
Specifications
| PARAMETER |
SYMBOL |
RATING |
UNIT |
| Voltage on VDD Supply Relative to VSS |
VDD |
-0.5 to 2.9 |
V |
| Voltage on VDDQ Supply Relative to VSS |
VDDQ |
-0.5 to VDD |
V |
| Voltage on Input Pin Relative to VSS |
VIN |
-0.5 to VDD+0.3 |
V |
| Storage Temperature |
TSTG |
-65 to 150 |
°C |
| Operating Temperature |
TOPR |
0 to 70 |
°C |
| Storage Temperature Range Under Bias |
TBIAS |
-10 to 85 |
°C |
*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VDDQ must not exceed VDD during normal operation.
DescriptionThe K7I163682B and K7I1161882B are 18,874,368-bits DDR Common I/O Synchronous Pipelined Burst SRAMs.They are organized as 524,288 words by 36bits for K7I163682B and 1,048,576 words by 18 bits for K7I161882B for K7I160882B.
Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,the data outputs are synchronized to the input clocks ( K and K ).Read data are referenced to echo clock ( CQ or CQ ) outputs.Read address and write address are registered on rising edges of the input K clocks.Common address bus is used to access address both for read and write operations.
The internal burst counter is fiexd to 2-bit sequential for both read and write operations.Synchronous pipeline read and late write enable high speed operations.Simple depth expansion is accomplished by using LD for port selection.Byte write operation is supported with BW0 and BW1 ( BW2 and BW3) pins for x18 ( x36 ) device.IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.
The K7I163682B and K7I161882B are implemented with SAMSUNG's high performance 6T CMOS technology and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
K7I161882B Data Sheet
