K5D5657ACM-F015

NOTE :
1.
Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability

The K5D5657ACM-F015 is a Multi Chip Package Memory which combines 256Mbit Nand Flash Memory and 256Mbit synchronous high data rate Dynamic RAM.

256Mbit NAND Flash memory K5D5657ACM-F015 is organized as 32M x8 bits and 256Mbit SDRAM is organized as 4M x16 bits x4 banks.In 256Mbit NAND Flash, a 528-Byte page program can be typically achieved within 200us and an 16K-Byte block erase can be typically achieved within 2ms. In serial read operation, a byte can be read by 50ns. DQ pins serve as the ports for address and data input/output as well as command inputs. Even the write-intensive systems can take advantage of FLASH¢s extended reliability of 100K program/erase cycles with real time mapping-out algorithm. These algorithms have been implemented in many mass storage applications.

In 256Mbit SDRAM, Synchronous design make a device K5D5657ACM-F015 controlled precisely with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

The K5D5657ACM-F015 is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. This K5D5657ACM-F015 is available in 107-ball FBGA Type.