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K4S64163LHR(B)E

Features: • 2.5V power supply.• LVCMOS compatible with multiplexed address.• Four banks operation.• MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave).• EMRS cy...

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SeekIC No. : 004383024 Detail

K4S64163LHR(B)E: Features: • 2.5V power supply.• LVCMOS compatible with multiplexed address.• Four banks operation.• MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Bur...

K4S64163LHR(B)E Data Sheet

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Part Number:
K4S64163LHR(B)E
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

•  2.5V power supply.
•  LVCMOS compatible with multiplexed address.
•  Four banks operation.
•  MRS cycle with address key programs.
      -. CAS latency (1, 2 & 3).
      -. Burst length (1, 2, 4, 8 & Full page).
      -. Burst type (Sequential & Interleave).
•  EMRS cycle with address key programs.
•  All inputs are sampled at the positive going edge of the system clock.
•  Burst read single-bit write operation.
•  Special Function Support.
      -. PASR (Partial Array Self Refresh).
      -. Internal TCSR (Temperature Compensated Self Refresh)
•  DQM for masking.
•  Auto refresh.
•  64ms refresh period (4K cycle).
•  Commercial Temperature Operation (-25°C ~ 70°C).
•  Extended Temperature Operation (-25°C ~ 85°C).
•  54Balls FBGA with 0.8mm ball pitch                                                     
        ( -RXXX : Leaded,   -BXXX : Lead Free).


Specifications

Parameter
Value
Unit
AC input levels (Vih/Vil)
0.9xVDDQ/ 0.2
V
Input timing measurement reference level
0.5 x VDDQ
V
Input rise and fall time
tr/tf = 1/1
ns
Output timing measurement reference level
0.5 x VDDQ
V
Output load condition
See Figure 2



Description

The K4S64163LHR(B)E is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits,fabricated with SAMSUNG's high performance CMOS technology. Synchronous design of K4S64163LHR(B)E allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.




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