Features: • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address• Four banks operation • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)• Al...
K4S640432D: Features: • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address• Four banks operation • MRS cycle with address key programs -. CAS latency (2 & 3...
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Features: • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed addre...
Features: • JEDEC standard 3.3V power supply• LVTTL compatible with multiplexed addres...
Features: • JEDEC standard 3.3V power supply• LVTTL compatible with multiplexed addres...
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
Parameter | Symbol | Value | Unit |
Voltage on any pin relative to VSS | VIN, VOUT | -1.0 ~ 4.6 | V |
Voltage on VDD & VDDQ supply relative to VSS | VDD, VDDQ | -1.0 ~ 4.6 | V |
Storage temperature | TSTG | -55 ~ +150 | |
Power dissipation | PD | 1 | W |
Short circuit current | IOS | 50 | mA |
The K4S640432D is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 4 bits, fabricated with SAMSUNGs high performance CMOS technol- ogy. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance mem-ory system applications.