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K4S560432H

Features: • JEDEC standard 3.3V power supply• LVTTL compatible with multiplexed address• Four banks operation• MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)• All ...

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SeekIC No. : 004382943 Detail

K4S560432H: Features: • JEDEC standard 3.3V power supply• LVTTL compatible with multiplexed address• Four banks operation• MRS cycle with address key programs -. CAS latency (2 & 3) ...

K4S560432H Data Sheet

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Part Number:
K4S560432H
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
  -. CAS latency (2 & 3)
  -. Burst length (1, 2, 4, 8 & Full page)
  -. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
• Pb/Pb-free Package
• RoHS compliant for Pb-free Package


Specifications

Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD 1 W
Short circuit current IOS 50 mA

Note :Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.




Description

The K4S560432H / K4S560832H / K4S561632H is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by 4 bits / 4 x 8,388,608 words by 8bits / 4 x 4,194,304 words by 16bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

 




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