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K4S51323PF-EF

Features: • 1.8V power supply.• LVCMOS compatible with multiplexed address.• Four banks operation.• MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave).• EMRS ...

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SeekIC No. : 004382935 Detail

K4S51323PF-EF: Features: • 1.8V power supply.• LVCMOS compatible with multiplexed address.• Four banks operation.• MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. B...

K4S51323PF-EF Data Sheet

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Part Number:
K4S51323PF-EF
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

•  1.8V power supply.
•  LVCMOS compatible with multiplexed address.
•  Four banks operation.
•  MRS cycle with address key programs.
         -. CAS latency (1, 2 & 3).
         -. Burst length (1, 2, 4, 8 & Full page).
         -. Burst type (Sequential & Interleave).
•  EMRS cycle with address key programs.
•  All inputs are sampled at the positive going edge of the system clock.
•  Burst read single-bit write operation.
•  Special Function Support.
        -. PASR (Partial Array Self Refresh).
        -. Internal TCSR (Temperature Compensated Self Refresh)
        -. DS (Driver Strength)
•  DQM for masking.
•  Auto refresh.
•  64ms refresh period (8K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• 2Chips DDP 90Balls FBGA( -MXXX -Pb, -EXXX -Pb Free).


Specifications

Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-1.0 ~ 2.6
V
Voltage on VDD supply relative to Vss
VDD, VDDQ
-1.0 ~ 2.6
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD
1.0
W
Short circuit current
IOS
50
mA



Description

The K4S51323PF-EF is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 32 bits,fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.




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