Features: • 3.0V & 3.3V power supply• LVCMOS compatible with multiplexed address• Four banks operation• MRS cycle with address key programs-. CAS latency (1, 2 & 3)-. Burst length (1, 2, 4, 8 & Full page)-. Burst type (Sequential & Interleave)• All inp...
K4M563233D-M(E)E/N/I/P: Features: • 3.0V & 3.3V power supply• LVCMOS compatible with multiplexed address• Four banks operation• MRS cycle with address key programs-. CAS latency (1, 2 & 3)-....
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Features: • 3.0V or 3.3V power supply.• LVCMOS compatible with multiplexed address....
Features: • 3.0V or 3.3V power supply.• LVCMOS compatible with multiplexed address....
Features: • 2.5V power supply.• LVCMOS compatible with multiplexed address.• Fou...
• 3.0V & 3.3V power supply
• LVCMOS compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (1, 2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle).
• Extended Temperature Operation (-25°C ~ 85°C).
• Inderstrial Temperature Operation (-40°C ~ 85°C).
• 90Balls DDP FBGA(-MXXX -Pb, -EXXX -Pb Free).
Parameter | Symbol | Value | Unit |
Voltage on any pin relative to Vss | VIN, VOUT | -1.0 ~ 4.6 | V |
Voltage on VDD supply relative to Vss | VDD ,VDDQ | -1.0 ~ 4.6 | V |
Storage temperature | TSTG | -55 ~ +150 | °C |
Power dissipation | PD | 1.0 | W |
Short circuit current | IOS | 50 | mA |
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
The K4M283233D is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits, fabricated with SAMSUNG¢s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.