IW4520B

PinoutSpecifications Symbol Parameter Value Unit VCCVINVOUTIINPDTstgTL DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storag...

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IW4520B Picture
SeekIC No. : 004381474 Detail

IW4520B: PinoutSpecifications Symbol Parameter Value Unit VCCVINVOUTIINPDTstgTL DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced...

floor Price/Ceiling Price

Part Number:
IW4520B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/3/13

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Product Details

Description



Pinout

  Connection Diagram


Specifications

Symbol
Parameter
Value
Unit
VCC

VIN

VOUT

IIN

PD

Tstg


TL
DC Supply Voltage (Referenced to GND)

DC Input Voltage (Referenced to GND)

DC Output Voltage (Referenced to GND)

DC Input Current, per Pin

Power Dissipation in Still Air, Plastic DIP+
SOIC Package+

Storage Temperature

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
-0.5 to +20

-0.5 to VCC +0.5

-0.5 to VCC +0.5

±10

750
500


-65 to +150

260
V

V

V

mA

mA

mA

mW




*Maximum Ratings are those values beyond which damage to the device may occur.Functional operation should be restricted to the Recommended Operating Conditions.+Derating - Plastic DIP: - 10 mW/ from 65° to 125
SOIC Package: : - 7 mW/ from 65° to 125



Description

The IW4520B Dual Binary Up-Counter consists two identical,internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For single-unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the CLOCK. The counters are cleared by high levels on their RESET lines.

The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the CLOCK input of the latter is held low.




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