ISO7220B

Features:


` 1, 5, 25, and 150-Mbps Signaling Rate Options
Low Channel-to-Channel Output Skew; 1 ns max
Low Pulse-Width Distortion (PWD); 1 ns max
Low Jitter Content; 1 ns Typ at 150 Mbps
` Typical 25-Year Life at Rated Voltage (see app. note SLLA197 and Figure 20)
` 4000-Vpeak Isolation, 560 V <sub>peak</sub> V<sub>IORM</sub>
UL 1577, IEC 60747-5-2 (VDE 0884, Rev 2),IEC 61010-1
50 kV/s Typical Transient Immunity
` Operates with 3.3-V or 5-V Supplies
` 4 kV ESD Protection
` High Electromagnetic Immunity
` 40 to 125 Operating Range


Application

` Industrial Fieldbus
Modbus
Profibus™
DeviceNet™ Data Buses
` Computer Peripheral Interface
` Servo Control Interface
` Data Acquisition


Specifications

				VALUE	UNIT
VCC Supply voltage(2), VCC1, VCC2				0.5 to 6	V
VI Voltage at IN, OUT				0.5 to 6	V
IO Output current				±15	mA
Electrostatic kV ESD discharge	Human Body Model	Electrostatic ischarge JEDEC Standard 22, Test Method A114-C.01	All pins	±4	kV
	Field-Induced-Charged Device Model	JEDEC Standard 22, Test Method C101		±1
	Machine Model	ANSI/ESDS5.2-1996		±200	V
TJ Maximum junction temperature				170

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.



Description

The ISO7220 and ISO7221 are dual-channel digital isolators. To facilitate PCB layout, the channels are oriented in the same direction in the ISO7220 and in opposite directions in the ISO7221. These devices have a logic input and output buffer separated by TI's silicon-dioxide (SiO₂) isolation barrier, providing galvanic isolation of up to 4000 V. Used in conjunction with isolated power supplies, these devices block high voltage, isolate grounds, and prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry.

A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation
barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or
resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received every 4 ms, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.

The small capacitance and resulting time constant provide fast operation with signaling rates available from 0
Mbps (dc) to 150 Mbps.(1)The A-, B- and C-option devices have TTL input thresholds and a noise filter at the
input that prevents transient pulses from being passed to the output of the device. The M-option devices have
CMOS V_CC/2 input thresholds and do not have the input noise-filter and the additional propagation delay.

These devices require two supply voltages of 3.3 V, 5 V, or any combination. All inputs are 5-V tolerant when supplied from a 3.3-V supply and all outputs are 4-mA CMOS.

These devices are characterized for operation over the ambient temperature range of 40 to 125.